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Long-form mentor guides on VLSI physical design, low-power implementation, timing and signoff by Tabish Iqbal. Free to read, with print-ready PDFs.
A SPEF file only tells you what the extractor found, not whether it found the right thing. This guide walks the whole path from a routed ICC2 block through StarRC extraction to an annotated PrimeTime session, covering corners and MMMC, run-quality checks, coupling capacitance, shorts and opens, and how to read a SPEF line by line. Written for an engineer who wants the signoff numbers to actually mean something.
29 Sept 2026Electromigration: What It Is, Why It Happens, and How Physical Design Fixes ItElectromigration is metal wearing out from the current running through it, not from age. I walk through the electron-wind mechanism, why it opens and shorts interconnect, Black's equation, and the layout techniques and ICC2/RedHawk commands I actually use to fix it before tapeout.
25 Sept 2026Static Timing Analysis: A Learning RoadmapMost people meet static timing analysis as a wall of commands and a report they cannot read. This guide takes the other route: fourteen stages, in order, from what the job actually is to what signing off means. Each one says where you are, what you will be able to do, the concept, the commands, the traps, and how long it takes. Every command is checked against the tool's own documentation.
25 Sept 2026The ECO Flow, Explained SimplyAn engineering change order is a repair to a design that is already placed and routed. This guide explains the whole flow in plain English: the three fixing commands, the order they run in and why, what the tool will and will not do for you, and how the change list reaches the layout team. Written for an engineer who has never run one.
25 Sept 2026Rush Current and the Daisy ChainTurning a power domain off is the easy half. Waking it pulls sixteen amperes out of your always-on grid, drops the supply for the neighbours, and can corrupt the retention state you powered down to keep. This guide works the arithmetic, builds the daisy chain that tames it, and then says plainly how many nanoseconds that fix costs you — and when power gating stops being worth doing at all.
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Full bundle ₹179 14 chaptersDesign Planning HandbookMaster VLSI physical design planning. Read 14 chapters free online or get the complete PDF bundle with floorplanning, power, CTS & timing budgeting.
Free to read · PDF ₹179 8 chaptersPnR Flow Mentor GuideFree 8-stage ICC2 PnR walkthrough: library setup to GDS output, with the real command driving each stage. Plus the full 8-chapter mentor guide.
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