Timing Constraints (SDC) Handbook

SDC in plain terms: what the file says and why every tool reads it

An SDC file is a plain-text Tcl script that tells synthesis, place-and-route and timing tools what the design is supposed to achieve. Without it a tool can calculate delays, but it cannot know which paths matter, how fast the clock runs or when data arrives at the ports. With it, static timing analysis can check every path against a requirement.

The five things an SDC file defines

A small example, line by line

create_clock -name CLK -period 2.0 -waveform {0 1.0} [get_ports clk]
set_clock_uncertainty -setup 0.10 [get_clocks CLK]
set_input_delay  0.6 -clock CLK [get_ports din*]
set_output_delay 0.5 -clock CLK [get_ports dout*]
set_driving_cell -lib_cell BUFX2 [get_ports din*]
set_load 0.05 [get_ports dout*]
set_false_path -from [get_ports rst_n]
set_multicycle_path 2 -setup -from [get_pins cfg_reg*/Q] -to [get_pins core/*/D]
set_multicycle_path 1 -hold  -from [get_pins cfg_reg*/Q] -to [get_pins core/*/D]

• Line 1 creates a clock called CLK on port clk with a period of 2.0 and a waveform that rises at 0 and falls at 1.0. If the library time unit is nanoseconds, that is a 500 MHz clock.
• Line 2 reserves 0.10 time units for jitter and margin on setup checks.
• Lines 3 and 4 say data arrives 0.6 time units after the clock edge at the inputs, and that logic outside the chip needs 0.5 time units at the outputs, so the paths inside must finish early enough to leave it.
• Lines 5 and 6 model a realistic driver on the inputs and a load on the outputs, so slews and delays at the boundary are not ideal.
• Line 7 removes the reset path from timing. Only do this when the reset is handled elsewhere, for example by a synchroniser.
• Lines 8 and 9 give a slow-changing configuration register two cycles for setup. The second line, the hold companion, moves the hold check back with it. Without it the tool keeps checking hold against an edge the data never uses, which creates a hold requirement that is almost impossible to meet.

Mistakes that cause most SDC problems

• Time units. SDC numbers carry no unit. The tool reads them in the time unit of the library, so a file written for picoseconds and read as nanoseconds is wrong by a factor of a thousand.
• A setup multicycle without its hold companion, as in the example above.
• False paths written too broadly. Excluding everything from a whole clock hides real paths. Scope the exception to the exact start and end points.
• Clocks that never reach their source. A generated clock whose master does not propagate to its source pin is not expanded, and the paths it should time end up unconstrained. Run a constraint check and review the unconstrained endpoints before trusting a clean report.
• Different constraints at different stages. Synthesis, place-and-route and signoff should read one agreed source, not three copies that drift apart.