📚 VLSI PHYSICAL DESIGN IMPLEMENTATION SERIES
The free 8-stage walkthrough below covers the full Nimbus-8 flow this guide follows — library setup through GDS output, with the real ICC2 command driving each stage. The paid 8-chapter book (693 pages, 146 vector figures) goes far deeper into each one, for whoever wants it.
🆓 FREE 8-STAGE WALKTHROUGH
Every stage of the Nimbus-8 flow this guide follows, with the real command that drives it. Each chapter goes far deeper — this is the map.
create_libEvery ICC2 session starts by opening a design library with create_lib, which holds one or more blocks plus the technology and reference-library data they share. Get this step wrong — a missing reference library, a mismatched technology file — and everything downstream inherits the error.
read_verilogWith the library open, the synthesized gate-level netlist comes in with read_verilog. A clean read with no unresolved references only proves the files were syntactically consumable — it is not proof the design is actually ready for floorplanning.
initialize_floorplaninitialize_floorplan lays down the die and core boundaries, rows, and routing tracks, and places any hard macros at explicit, reproducible coordinates. Most of a design’s eventual congestion and timing headroom gets decided here, long before placement runs.
compile_pgPower planning defines the P/G ring and mesh pattern, then compile_pg builds it into real metal shapes and switch connectivity. An uncompiled or too-thin power network shows up later as IR drop or a missing power pin, not as an obvious floorplan error.
place_optplace_opt runs placement in stages — legalization, timing- and congestion-driven placement, and concurrent clock/data optimization. The reports at each stage, not just a clean exit code, are what tell you whether the design is ready for CTS.
clock_optclock_opt builds and balances the clock tree, closing skew and insertion delay across every sink. This is where multi-source clock trees and the clock QoR report become the numbers you actually watch, not the placement view.
route_auto / route_optroute_auto lays down the physical wires — full on a first pass, incremental afterward — and route_opt then optimizes the routed design for timing at whatever effort level the remaining slack calls for. Most of the design’s final setup/hold picture is decided for real here.
write_gdsChip finishing adds metal fill and checks DFM rules, and the flow ends with write_gds streaming out the final GDSII against an explicit layer map — with a decision about whether dummy fill ships in the same file or a separate one.
From an empty library setup to a legally placed, timing-aware design — importing the netlist and power intent, sizing the die and placing macros, and driving the five stages of place_opt to a placement the rest of the flow can build on.
Library and technology setup, netlist and power-intent import, timing setup, and the readiness checks that gate entry into floorplanning.
Die and core geometry, rows and tracks, macro placement, power-planning interfaces, and the arithmetic that turns a target density into an achievable one.
The five place_opt stages, legalization, timing/congestion-driven placement, concurrent clock/data optimization, and the reports that clear a design for CTS.
Building and balancing the clock, committing every net to metal, and turning a routed, timing-closed database into something a foundry can actually build.
What changes at CTS: defining and balancing clock trees, clock_opt, multisource clock trees, reading a clock QoR report, and troubleshooting by symptom.
Routing strategy, the standard global/detail-route flow, routing with Custom Router, postroute optimization, and the stage-exit checklist to chip finishing.
Tap, boundary and filler cells, redundant vias, critical-area reduction, metal density/fill, and signoff DRC with IC Validator In-Design, ending in stream-out.
The two things that decide whether a design tapes out on schedule: splitting a design too big to close flat into blocks that close independently, and changing a closed database without disturbing it.
Partitioning and block definition, pin assignment and feedthroughs, timing budgeting, abstract views and ETMs, and top-level closure for a hierarchical design.
Identifying what changed, the five ECO flows, spare cells/freeze silicon, the PrimeTime signoff loop, ECO Fusion, and proving an ECO disturbed nothing else.
This guide covers how a chip is built — library setup, placement, CTS, routing, chip finishing, and ECO. Before any of that starts, Design Planning covers how it is planned: floorplan, macros, power grid, clock trunks, and timing budgets.