How do you prove clocks reach sequential clock pins?

Short Answer

" The standard tool for this is a no_clock check — most STA/PD tools flag any register whose clock pin has no active clock propagating to it, which usually means either a genuine connectivity bug (a broken net, an unintended tie-off) or a legitimate case like a register that's intentionally clocked by a gated/disabled clock in the current mode.

Technical Explanation

• "
• The standard tool for this is a no_clock check — most STA/PD tools flag any register whose clock pin has no active clock propagating to it, which usually means either a genuine connectivity bug (a broken net, an unintended tie-off) or a legitimate case like a register that's intentionally clocked by a gated/disabled clock in the current mode.
• Run targeted report_clock / all_registers -clock_pins style reports and cross-reference against the expected register groups from your design spec — if a block is supposed to have, say, 200 registers on clk_core, verify that count actually shows up, not just that some registers do.
• Trace a few representative paths with report_timing -from <clock source> -to <register CP> to confirm the logical arc is actually intact end-to-end, not just that a clock object exists somewhere in the hierarchy.
• Treat the whole exercise as a readiness gate: the output should be a list of named clocks, named register groups, and a clean no_clock report — something a reviewing engineer could rerun from the same handoff data and get the identical result, not something that depended on you eyeballing a schematic.
• Catching a missing clock connection here, before CTS and routing, is dramatically cheaper than discovering a functionally dead register bank during silicon bring-up.

What To Check

• Warning sign: A primary clock is reported, yet a gated branch or generated domain never reaches its registers.
• Inspect: Compare one named object across the related reports; the same object should tell a consistent story.
• Correct: Repair clock/gating/generated-clock intent or netlist connectivity, then compare affected register groups.

Healthy, Suspicious & Hard-stop Results

• Expected: Use no_clock checks and targeted timing reports to correlate expected register groups with clock propagation through logical arcs.
• Stop before floorplanning when required logic or timing coverage is missing or unexplained.

What The Interviewer Is Testing

Be ready to explain why this matters before floorplanning.

Follow-up Question & Model Response

Model response: “I would save the report, inspect one affected object in the correct block and scenario, and make or request this correction. ”