IntermediateQuestion 109 of 222

How do you constrain which metal layers a clock tree is allowed to route on, and can you be more specific than "the whole tree"?

From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

set_clock_routing_rules -min_routing_layer M4 -max_routing_layer M7 applies to all clock trees by default, but you can scope it to specific clocks (-clocks), or to specific net types within the tree using -net_type root|sink|internal -- root nets run from the clock root to the first branch, internal nets run from there toward sinks, and sink nets connect directly to leaf sinks.

Technical Reference DiagramHow do you constrain which metal layers a clock tree is allowed to route on, and can you be more specific than "the whole tree"?

Technical Explanation

  • set_clock_routing_rules -min_routing_layer M4 -max_routing_layer M7 applies to all clock trees by default -- a global layer constraint unless scoped down.
  • -clocks scopes the constraint to specific clocks rather than the whole design.
  • -net_type root|sink|internal scopes to a specific portion of the tree structurally: root nets (clock root to first branch), sink nets (connecting directly to leaf sinks), and internal nets (everything in between).
  • You can also assign an NDR to clock nets directly via -rules <rule_name> instead of, or alongside, layer bounds.

Common Mistake

The Trap: Applying a single global layer constraint to the entire clock tree when the actual congestion or EM concern only applies to root nets or sink nets specifically -- over-constraining the rest of the tree unnecessarily.

Follow-up Question & Model Response

"Why would root nets specifically be the most likely candidates for a tighter layer or NDR constraint?"

Candidate Model Response: Root nets carry the most fanout and the highest current demand of any segment in the tree, making them the most likely candidates for EM concerns or congestion issues that a tighter layer or NDR constraint would specifically address.

Practical Example

Debug Scenario: EM concerns on the highest-current segment of a clock tree (the root net, carrying the most fanout) are addressed with set_clock_routing_rules -net_type root -min_routing_layer M6, leaving sink and internal nets unconstrained.

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