IntermediateQuestion 27 of 222

What does dp_pre_floorplan actually prove?

From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide

Short Answer

It's tempting to treat dp_pre_floorplan as a green light that says "your design is floorplan-ready" — it isn't. It's a narrow, specific technology-readiness check, and confusing "passed dp_pre_floorplan" with "ready to floorplan" is a common and costly mistake. Concretely, it checks technology-file information and routing-layer directions — including confirming that both horizontal and vertical routing layers actually exist in your tech setup.

Technical Reference DiagramWhat does dp_pre_floorplan actually prove?

Technical Explanation

  • Think of it like checking that your kitchen has both a stove and a sink before you start cooking — necessary, but it tells you nothing about whether you actually have the ingredients (netlist, constraints, macro placement, power planning) ready to go.
  • Passing it means your technology data is internally sane enough to attempt a floorplan. It says nothing about whether your die/core sizing, macro placement, power grid, or timing constraints are actually correct or complete.
  • Treat it as step zero of readiness, not the finish line — you still need the full floorplan review checklist (die/core geometry, rows, macro legality, channels, PG reservation, congestion/timing evidence) before calling a floorplan reviewable.

What To Check

  • Warning sign: A passing dp_pre_floorplan result is misreported as proof that the netlist and SDC are correct.
  • Inspect: Compare one named object across the related reports; the same object should tell a consistent story.
  • Correct: Run structural, unbound, SDC, clock, scenario, exception, and timing-health checks separately.

Command Checks & Actions

  • check_design -checks {dp_pre_floorplan}: runs the selected design-readiness checks
  • get_design_checks: lists checks supported by the installed release

Run the commands in order. Each line answers a separate part of the check.

Healthy, Suspicious & Hard-stop Results

  • Expected: It checks technology-file information, layer directions, and the presence of horizontal and vertical layers; it is only one readiness component.
  • Stop before floorplanning when required logic or timing coverage is missing or unexplained.

Common Mistake

The Trap: Do not assume the check passed just because ICC2 continued. Fix or narrowly justify the named objects, then rerun the same command.

What The Interviewer Is Testing

Be ready to explain why this matters before floorplanning.

Follow-up Question & Model Response

Model response: “I would save the report, inspect one affected object in the correct block and scenario, and make or request this correction. ”

PnR Flow Mentor Guide

Read the complete 8-chapter PnR Flow Mentor Guide free on the web — library setup through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO, all the way to stream-out.

Offline PDF Bundle

Want all 1109 questions offline?

Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.

See what's inside the bundle
PnR Flow Physical Design Mentor Guide — eight chaptersPnR Flow Mentor GuideEight chapters, library setup through to stream-out.