What does set_isolate_ports actually do, and which ports does it deliberately skip?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
set_isolate_ports inserts a buffer/inverter pair at specified ports for model accuracy -- {in3 out1} isolates those two ports; -driver LIBCELL_BUFF picks a specific driver cell; -type inverter picks an inverter pair instead. It is NOT applied to bidirectional ports, ports defined as clock sources or power pins, or ports connected to dont_touch nets -- these are deliberate, documented exclusions, not gaps to work around.
Technical Explanation
- set_isolate_ports inserts a buffer/inverter pair at specified ports specifically for model accuracy -- e.g. set_isolate_ports {in3 out1} isolates those two named ports.
- -driver LIBCELL_BUFF picks a specific driver cell for the isolation buffer; -type inverter picks an inverter pair instead of a buffer pair.
- It is NOT applied to bidirectional ports, ports defined as clock sources or power pins, or ports connected to dont_touch nets -- these are deliberate, documented exclusions.
- -force overrides in cases where the isolation would otherwise be skipped for a reason the user wants to override anyway.
Common Mistake
The Trap: Expecting set_isolate_ports to isolate every port you name, without checking whether any of them fall into the documented exclusion categories (bidirectional, clock source, power, or dont_touch-net-connected) that silently skip isolation unless -force is used.
Follow-up Question & Model Response
"Why would isolating a clock source port specifically be excluded by default, rather than treated the same as an ordinary data port?"
Candidate Model Response: Because inserting a buffer/inverter pair at a clock source would add real, uncharacterized delay right at the clock's entry point into the design -- exactly the kind of change that would corrupt the clock's own timing model rather than improving analysis accuracy, which is the opposite of what port isolation is meant to achieve.
Practical Example
Debug Scenario: set_isolate_ports {clk_in data_out} is called expecting both ports isolated, but only data_out actually gets a buffer pair inserted -- clk_in was silently skipped because it's a defined clock source port, one of the documented default exclusions.
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