What does the short-circuit (transition) power formula capture that dynamic power doesn't, and what specifically controls it during placement?

Short Answer

Transition (short-circuit) power occurs when the input transition is slow enough that NMOS and PMOS conduct simultaneously, creating a direct supply-to-ground path that contributes nothing to gate operation: Pt = I^2 * (Rp + Rn). This is a genuinely different mechanism from dynamic (switching) power -- it's wasted current from both transistors briefly conducting together, not useful charge/discharge of a load capacitance. Reduce it by controlling max input transitions during placement, or specifying max allowable transition per cell in the library.

Technical Explanation

• Transition (short-circuit) power occurs when the input transition is slow enough that NMOS and PMOS conduct SIMULTANEOUSLY -- creating a direct supply-to-ground current path that contributes NOTHING to actual gate operation.
• Formula: Pt = I^2 (Rp + Rn) -- current squared times the sum of PMOS and NMOS resistance, a genuinely different mechanism from dynamic power's V^2sum(fi*Ci).
• This is fundamentally wasted current, not useful charge/discharge of a load capacitance -- dynamic power is the cost of DOING the switching work; short-circuit power is pure overhead from doing it too slowly.
• Reduce it by controlling MAX INPUT TRANSITIONS during placement, or by specifying max allowable transition per cell directly in the library -- the fix targets slew, not load capacitance, which is exactly why it's a distinct lever from dynamic power reduction.

Formula Or Decision Rule

Pt = I^2 (Rp + Rn) -- distinct from Pd = V^2sum(fi*Ci); short-circuit power is driven by slow input transitions causing simultaneous PMOS/NMOS conduction, not by switching activity or load capacitance directly.

What To Check

• Warning sign: a design shows higher-than-expected total power despite load capacitance already being well-controlled via placement-stage limits.
• Inspect: check whether input transitions (slew) across the design are being adequately controlled -- an uncontrolled slow transition can drive real short-circuit power that load-capacitance limiting alone wouldn't address.
• Correct: apply max-transition limits during placement (or via library-level max-transition specification) specifically to address this separate power mechanism.

Healthy, Suspicious & Hard-stop Results

• Expected: input transitions across the design stay within controlled limits, keeping short-circuit power contribution low, verified via report_power's breakdown.
• Investigate: total power is higher than expected despite load capacitance being well-controlled -- check input transition control specifically, since short-circuit power has its own independent root cause.
• Stop: power optimization effort is focused entirely on load-capacitance/dynamic-power levers while input transitions remain uncontrolled, ignoring the separate short-circuit power mechanism entirely.

What The Interviewer Is Testing

Whether you know short-circuit power is a genuinely distinct mechanism from dynamic power, with its own formula and its own specific fix (transition control), not just "another kind of switching power."