Complete VLSI Physical Design & Timing Signoff Library

STA Handbook (10 Chapters)

The definitive guide to static timing analysis foundations, PrimeTime workflows, and silicon signoff closure.

• Setup and hold check mechanics & equations
• On-Chip Variation (OCV, AOCV, POCV) & LVF derates
• Clock Reconvergence Pessimism Removal (CRPR / CPPR)
• Crosstalk delay, glitch noise, and signal integrity
• PrimeTime timing report interpretation & ECO closure

SDC Timing Constraints (9 Chapters)

Master Synopsys Design Constraints from create_clock to final complex I/O boundary signoff.

• Primary clocks, generated clocks & divide-by-N waveforms
• Asynchronous, exclusive & physical clock grouping
• Input and output interface delay modeling (set_input_delay)
• False path and multicycle path exception precedence
• Managing constraints across synthesis, CTS, and routing

MMMC Timing Signoff Masterclass (10 Chapters)

Master Multi-Mode Multi-Corner timing closure across complex multi-scenario semiconductor SOCs.

• Operating modes vs PVT corners distinction
• Analysis view creation, activation, and optimization weights
• SPEF parasitic extraction variation across RC corners
• Multi-scenario DMSA analysis in PrimeTime & Tempus
• Preventing ECO side effects across active views

Low-Power Physical Design Basics (9 Chapters)

Essential silicon foundations of power dissipation, dynamic vs leakage power, and UPF power intent.

• Dynamic, switching, and static leakage power mechanics
• Standard cell power characterization and Liberty models
• Memory, macro, and clock-tree power optimization
• Multi-Vt optimization and power gating basics
• Specifying power intent with IEEE 1801 UPF

Low-Power Tool Guide & UPF in ICC2 (11 Chapters)

Complete step-by-step practical guide to writing and implementing UPF power architectures in ICC2.

• Power domains, voltage areas, and supply networks in UPF
• Isolation cells, level shifters, and power switch sizing
• State retention flip-flops and save/restore sequencing
• Power State Tables (PST) and early structural verification
• Writing production UPF scripts from scratch for ICC2

Signoff Academy (13 Guides)

Industry-standard physical and electrical signoff checklists and gate review criteria before tapeout.

• DRC, LVS, and Antenna verification with IC Validator
• Metal fill and density signoff rules
• Electrical Rule Checking (ERC) and ESD protection
• Logic Equivalence Checking (LEC) with Formality
• Comprehensive ASIC Signoff Cheat Sheet

Design Planning & Floorplanning (14 Chapters)

From die sizing and macro placement to hierarchical block commit, power mesh, and timing budgeting.

• Die/core sizing, aspect ratio, and utilization targets
• Macro placement, halos, keepouts, and channel budgeting
• Power mesh distribution and global routing corridors
• Early CTS and clock trunk latency management
• Hierarchical design commit and timing budgeting

ICC2 Implementation Mentor Guide (8 Chapters)

One continuous Nimbus-8 design carried from library setup through placement, CTS, routing, chip finishing, hierarchical implementation, and ECO signoff.

• Placement and optimization with the five place_opt stages
• Clock tree synthesis, skew, and insertion delay
• Routing, postroute optimization, and chip finishing/DFM
• Hierarchical implementation and block partitioning
• ECO flow and PrimeTime signoff loops

All 8 Collections Bundle (84 Chapters)

Get instant access to all eight comprehensive eBook collections for a single discounted price of ₹1,237.

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