What is setup timing, and what is hold timing, in plain terms?
From PDVerse MMMC Interview Masterclass, part of the pdVerse Mentor Series
Direct answer
Setup timing is a maximum-delay check verifying that data arrives before the next clock edge (N+1). Hold timing is a minimum-delay check verifying that data remains stable long enough not to corrupt data captured on the current clock edge (N).
Mentor explanation
Setup and hold checks protect opposite boundaries of the flip-flop sampling window.
Key terms
- Setup check — launch edge N to capture edge N+1 (one full period later); frequency-dependent, so violations can be mitigated by reducing clock frequency.
- Hold check — launch edge N to capture edge N (same cycle); frequency-independent, so changing clock frequency has zero effect on hold slack.
- Worst setup conditions — slow process, low voltage, high temperature, max RC.
- Worst hold conditions — fast process, high voltage, low temperature, min RC.
Hold is a same-cycle race condition. Because clock period cancels out in the hold equation, an unfixed hold violation in silicon is fatal and cannot be worked around by slowing down the clock.
Practical example
Setup vs Hold Comparison Matrix:
+--------------------+--------------------------------+--------------------------------+
| Parameter | Setup Check (Max Delay) | Hold Check (Min Delay) |
+--------------------+--------------------------------+--------------------------------+
| Launch/Capture | Edge N -> Edge N+1 | Edge N -> Edge N (Same edge) |
| Target Constraint | Must arrive BEFORE Tsetup | Must remain AFTER Thold |
| Frequency Impact | Dependent (Fixable by slowing) | Independent (Fatal in silicon!)|
| Worst Corner | SSG / Low Vdd / High Temp / RCmax | FFG / High Vdd / Low Temp / RCmin|
| Typical Fix | Upsize gates, buffer insertion | Add delay buffers to data path |
+--------------------+--------------------------------+--------------------------------+Interview trap
Suggesting that a hold violation can be resolved by lowering the clock frequency. Hold checks are frequency-independent same-edge comparisons; lowering frequency does not alter hold slack.
Key takeaways
- Setup checks maximum path delay across one clock period (T_period).
- Hold checks minimum path delay at the same clock edge (T = 0) and is independent of clock frequency.
- Unfixed hold violations cause catastrophic silicon failure that cannot be bypassed by reducing frequency.
Self-check: can you answer this aloud?
Try a 45-second answer using this structure:
- State the direct answer.
- Explain the timing or physical reason.
- Name one caveat.
- Say how you would verify it in a real flow.
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