How do buses and differential pairs change pin planning?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
A bus isn't just "a bunch of individual pins" — related signals need to reach the block boundary in an order the router can continue naturally, meaning bit 0 through bit N should land in a sequence that doesn't force the router to cross wires just to sort them out downstream. Bit ordering matters concretely: if bus bits arrive at the boundary scrambled relative to their destination order inside the block, you get extra jogs, more vias, and congestion right at the pin — exactly the kind of local congestion that's expensive to fix later.
Technical Explanation
- Differential pairs need something buses don't: the two complementary signals (P/N) must be routed as a matched pair — same length, ideally shielded or at least consistently spaced, so the differential signal integrity that the whole point of using a diff pair depends on isn't quietly broken by pin placement.
- Watch two specific traps: corner crowding (cramming a wide bus or several diff pairs into a chip corner where routing resources are naturally scarcer) and arbitrary spreading (evenly distributing bus bits across a whole side "for balance" without regard to internal destination order, which undoes the ordering benefit).
- In practice, pin planning for buses/diff pairs should account for: protocol grouping (keep a protocol's signals together), bit order, shielding needs, which layer direction the bus prefers, keeping clear of corner keepouts, realistic pin-to-pin spacing, how this maps to the package (BGA ball map), and physical affinity to the macro or I/O cell the bus actually connects to.
Formula Or Decision Rule
Decision rule: preserve required relationships while leaving legal, low-detour access on both sides of the boundary.
What To Check
- Warning sign: A bus is reversed or a differential pair is separated by unrelated pins.
- Inspect: choose one affected region, macro, row, pin, path, or net and trace the physical cause.
- Correct: Correct the bundle/order constraints and re-place only the affected pins, then recheck.
Command Checks & Actions
- place_pins -pins <pin_collection> -legalize: places or legalises targeted pins
- check_pin_placement: checks pin-placement legality and access-related conditions
- report_pin_placement -pins <pin_collection>: reports pin layer, side, and offset
Run only the commands needed for this question. Save the report with the floorplan version and analysis context.
Healthy, Suspicious & Hard-stop Results
- Healthy: Buses need deliberate ordering and corridor width; differential pairs need paired routing opportunity and consistent constraints. Both can be harmed by corner crowding or arbitrary spreading.
- Hard stop: required legality or physical feasibility is missing or unexplained.
Common Mistake
The Trap: Do not hide the symptom with an arbitrary utilisation, halo, channel, blockage, pin move, or die-size change.
What The Interviewer Is Testing
” to measurable physical evidence and an owned correction.
Follow-up Question & Model Response
"* Candidate Model Response: Model response: “I would change it if the same controlled rerun shows that a bus is reversed or a differential pair is separated by unrelated pins. ”
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