IntermediateQuestion 73 of 222

How should hierarchical block pins be placed?

From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide

Short Answer

A block pin is a doorway shared between the parent design and the child block โ€” both sides need usable, legal access to it, not just the child block's own internal convenience. "

Technical Reference DiagramHow should hierarchical block pins be placed?

Technical Explanation

  • "
  • Use pin constraints and guides to steer where pins land, exclude nets that shouldn't be pin-placed together, legalize the targeted pin group, and then verify with an exact report of layer/side/offset per pin โ€” don't just eyeball the layout.
  • Think about routing corridors and pin bundles at the top level before locking pin positions โ€” placing pins without considering the parent's routing plan just moves the congestion problem up one hierarchy level.
  • If a pin is meant to feed through the block without being used internally (a feedthrough), that intent needs to be explicit โ€” an accidental feedthrough-looking pin placement can silently change what the tool assumes about the net.

Formula Or Decision Rule

Decision rule: a pin location must work for both internal and external routing.

What To Check

  • Warning sign: Pins are evenly spaced but force top-level detours or internal crossovers.
  • Inspect: choose one affected region, macro, row, pin, path, or net and trace the physical cause.
  • Correct: Regroup, reorder, re-layer, or move the pins and rerun pin/access and congestion checks.

Command Checks & Actions

  • place_pins -cells <cells> -pins <pins> -legalize: places or legalises targeted pins
  • report_pin_placement -pins <pins> -format {layer side offset}: reports pin layer, side, and offset

Run only the commands needed for this question. Save the report with the floorplan version and analysis context.

Healthy, Suspicious & Hard-stop Results

  • Healthy: Place block pins on legal sides, layers, tracks, and offsets according to top-level dataflow, routing corridors, bundles, and feedthrough intent.
  • Hard stop: required legality or physical feasibility is missing or unexplained.

Common Mistake

The Trap: Do not hide the symptom with an arbitrary utilisation, halo, channel, blockage, pin move, or die-size change.

What The Interviewer Is Testing

โ€ to measurable physical evidence and an owned correction.

Follow-up Question & Model Response

"* Candidate Model Response: Model response: โ€œI would change it if the same controlled rerun shows that pins are evenly spaced but force top-level detours or internal crossovers. โ€

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