When does CTS actually split a clock cell, and how can you tell a split cell apart from the original?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
split_clock_cells splits a clock cell to fix a DRC violation by dividing its load between two cells. A cell is NOT split if it has no DRC violations, has dont_touch/size_only/fixed placement, or would require punching a new port on a frozen power domain or block boundary. New cells are named <original_cell_name>_split_<integer>, and settings/constraints are copied from the original.
Technical Explanation
- split_clock_cells splits a clock cell to fix a DRC violation, dividing its load between two cells instead of one overloaded one.
- A cell is NOT split if it has no DRC violations to begin with, has dont_touch/size_only/fixed placement, or would require punching a new port on a frozen power domain or block boundary (set_freeze_ports).
- New cells from a split are named <original_cell_name>_split_<integer>, and the split cells inherit the original's settings and constraints -- not a fresh, unconstrained pair.
Common Mistake
The Trap: Assuming every clock cell with high fanout automatically gets split -- splitting only happens to fix an actual DRC violation, not as a general high-fanout precaution.
Follow-up Question & Model Response
"If a clock cell has a real DRC violation but also has dont_touch set, what happens?"
Candidate Model Response: The DRC violation persists uncorrected -- dont_touch takes priority over the split operation, so the cell stays overloaded until dont_touch is deliberately cleared or a different fix (resizing, rerouting) is applied instead.
Practical Example
Debug Scenario: A heavily loaded clock buffer shows a max-capacitance violation. split_clock_cells divides its loads into two new cells, U1/ICG3_split_1 and U1/ICG3_split_2, each taking half the original fanout and inheriting the original buffer's constraints.
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