Level 1: Foundations

Beginner PnR (Place & Route) Interview Questions

Build solid foundations in physical design inputs, standard cell models, technology data, units, and manufacturing grids.

0 of 187 marked complete

Want all 1109 answers offline as 4 PDF books?

See the 4-book bundle · ₹349Physical Design & Planning HandbookComplete library

What to practise at this level

Build solid foundations in physical design inputs, standard cell models, technology data, units, and manufacturing grids.

  1. 01 What are the main inputs required for physical design?Beginner: Physical design needs six real inputs, not just a blueprint: the netlist (what to build), timing library models (how fast and how much power each cell uses), physical library views (each cell's real dimensions and pins), technology data (the manufacturing grid, layers, vias, rules), RC tech models (how the wiring itself behaves electrically), and SDC (the speed target and legal timing exceptions) — like handing a contractor a full kit, not just a blueprint. The netlist is only cell instances and connections — nothing about timing or size unless the matching logical library models are loaded too.
  2. 02 What does a gate-level netlist contain?Beginner: A gate-level netlist describes your circuit purely as connectivity — instances of library cells or modules, wired together by nets — it captures *what connects to what*, not where anything physically sits or what shape the wires will eventually be. Think in terms of a simple electrical vocabulary: a cell is a component, a pin is its terminal, a net is a wire connecting terminals, and an instance is one particular usage of a cell (the same inverter cell might be instantiated hundreds of times under hundreds of different instance names).
  3. 03 How is RTL different from the netlist used for place and route?Beginner: RTL is intent — "add these two registers" — while the netlist is the actual implementation synthesis chose: specific gates, specific drive strengths, specific structures. RTL alone can't tell you which adder topology or cell variants got used; only the mapped netlist exposes the real instances and connectivity that physical design can place and route.
  4. 04 What information does a Liberty timing library provide?Beginner: A Liberty (`.lib`) library is essentially a cell's complete behavioral datasheet — how it behaves electrically and logically under specific characterized conditions — used for timing, power analysis, and picking legal cells during synthesis/optimization. It is not a placement or layout drawing. Core content includes: cell and pin names, pin directions, Boolean function, input pin capacitance, timing arcs, output transition behavior, and electrical limits (max cap, max transition).
  5. 05 What is the difference between LEF and DEF?Beginner: LEF is the rulebook and parts catalog — it describes reusable technology data (layers, vias, sites) and cell-level physical abstractions (a cell or macro's boundary, pin geometry, routing obstructions), independent of any specific chip. DEF is the actual layout of one particular design — where instances actually sit, how they're oriented, the die area, rows, tracks, blockages, and (depending on stage/export settings) routing.
  6. 06 What are NDM, reference libraries, and design libraries in ICC2?Beginner: NDM is ICC2's library/database framework — the container system, not a specific library itself. Reference libraries are the toolbox: standard cells, macros, anything reusable that your design draws from.
  7. 07 What does the technology file contain, and why is it necessary?Beginner: The technology file is the process "dictionary" — units, layers, vias, placement sites, and routing rules — that gives every coordinate and dimension a consistent, legal meaning. Without it, a netlist can be logically perfect while being physically impossible to build: the router doesn't know what layers exist or how to legally hop between them, and the placer doesn't know a grid compatible with the cells.
  8. 08 What is SDC, and what should a physical-design SDC contain?Beginner: SDC is the design's stated timing contract: which clocks exist, which paths matter, and under what electrical assumptions they get checked. A solid handoff SDC defines primary and generated clocks with real periods and waveforms, input/output delay budgets, sensible transition or driving-cell/load assumptions at the boundary, and any timing exceptions — with justification, not just wildcards.
  9. 09 Which units are used in physical design, timing, and power?Beginner: A number without its unit is just noise — PD juggles distance, time, capacitance, resistance, voltage, current, and power, often in different units across different files. Distance is usually micrometers (um) or nanometers (nm) — 1 um = 1000 nm. Time is nanoseconds or picoseconds — 1 ns = 1000 ps. Capacitance is picofarads or femtofarads — 1 pF = 1000 fF.
  10. 10 What are database units, and how do you convert DEF coordinates?Beginner: Database units (DBU) are just an integer scaling factor that lets DEF store every coordinate as a whole number instead of a floating-point micron value — floating point invites rounding drift across a huge file, integers don't. The DEF header states the scale, e.g. `UNITS DISTANCE MICRONS 2000 ;` means 2000 DBU = 1 micron. So converting is simple division: `microns = DBU_value / 2000`. Going the other way, multiply microns by the scale factor to get DBU.
  11. 11 What is the difference between wire width, spacing, and pitch?Beginner: Width is how thick the wire itself is, measured straight across it. Spacing is the empty gap between the edge of one shape and the edge of its neighbor.
  12. 12 What is the purpose of the pre-floorplan sanity gate?Beginner: This gate checks whether the imported, linked netlist and its timing intent are believable enough to start floorplanning — a "do we trust this handoff" checkpoint, not a quality review. It's deliberately narrow in scope: it says nothing about placement quality or final timing results, only about whether the starting point is sound.
  13. 13 Which inputs must a physical-design engineer verify at this gate?Beginner: This gate is really a verification checklist run before you commit to floorplanning: netlist, SDC, top module name, handoff revision, logical libraries, reference/technology setup, modes/corners/scenarios, and whatever synthesis or STA summaries the upstream team can hand you. Every one of these should resolve to named, real objects you can point to — a listed clock that actually exists, a top name that actually matches the loaded hierarchy — not just files that happened to load without error.
  14. 14 Why record a manifest and file checksums?Beginner: A manifest is the packing list that comes with every design handoff — it tells the receiving engineer exactly what revision, corner, mode, and producer each input file represents, so nobody has to guess. Without it, "the netlist" or "the SDC" is ambiguous — there could be five versions floating around a project, and the wrong one silently loaded gives you a run that looks fine but is quietly analyzing the wrong design.
  15. 15 How do you confirm the correct top module and netlist revision?Beginner: The top module is the boundary ICC2 believes it's implementing — get this wrong and every count, report, and timing number downstream can look perfectly reasonable while describing the wrong design. Confirming it means matching four things against the handoff record and synthesis summary: the current block, the expected top name, the hierarchy structure, and the cell/instance inventory.
  16. 16 Why check libraries and units before reading timing numbers?Beginner: A library gives every cell its meaning — what a NAND2X4 actually *does* electrically and logically — while units give every number its scale. You need both settled before a timing number means anything at all. If the wrong library (or wrong corner within the right library) is loaded, delay numbers can look completely plausible while describing a cell that isn't the one actually in your design.
  17. 17 What is the difference between importing and linking a netlist?Beginner: Reading a Verilog netlist (`read_verilog`) is like reading an address book — it creates the names of design objects (instances, ports, nets) and records how they're supposed to connect, but it doesn't verify any of those references actually resolve to something real. Linking is the follow-up step where ICC2 actually finds the real definition for every instantiated cell — whether that's a leaf-level library cell or a lower-level design module — and connects the netlist's abstract references to concrete objects.
  18. 18 Why must current_block be checked before every sanity run?Beginner: Think of `current_block` as the "you are here" pointer in ICC2 — almost every command (`get_cells`, `report_timing`, `place_opt`, you name it) silently operates on whatever block is currently active, not the block whose name you typed in your last `open_block`. If you have several blocks open in the same session (a hierarchical flow, a sub-block plus the top level, or two design revisions loaded for comparison), a query can run cleanly against the wrong block and return a perfectly formatted, completely irrelevant answer.
  19. 19 What does an unresolved reference mean?Beginner: An unresolved reference means an instance in the netlist points to a module or library cell that the tool's currently loaded reference context simply doesn't have. ICC2 knows something was instantiated there — it just doesn't know what object is supposed to implement it.
  20. 20 When can a black box be intentional?Beginner: A black box is only legitimate when it's a deliberate, methodology-sanctioned abstraction — not simply a missing reference library that nobody noticed. The classic legitimate case: a hard macro or IP block delivered as a timing/physical abstract (`.lib`/`.lef`/frame view) rather than full internal detail, because the internals aren't needed (or aren't allowed to be seen) at this stage of the flow.
  21. 21 What does check_netlist contribute before floorplanning?Beginner: Linking (binding the netlist against your libraries) only tells you the tool found a definition for every instance — it proves the netlist *parses*, not that it makes sense. `check_netlist` goes a level deeper: it looks for structural problems that can survive linking perfectly cleanly — things like multiple drivers on one net, unconnected/dangling pins, or other connectivity defects that don't stop the netlist from loading but will definitely cause trouble later.
  22. 22 How should undriven and unloaded objects be reviewed?Beginner: A driver produces a signal; a load consumes it. An undriven object has no valid source feeding it, and an unloaded output has nowhere meaningful to go. Neither is automatically a bug — both can be legitimate at a design boundary (an unused output pin, an intentionally tied-off input) or they can be evidence that connectivity got lost somewhere during synthesis or netlist editing.
  23. 23 What is the difference between a dangling connection and a no-load net?Beginner: A **dangling connection** is a hard disconnect: a pin or port that simply isn't wired to anything on one side — think of an unplugged cable end. It usually shows up as an unconnected pin in `report_design` or a floating net in LVS. A **no-load net** is more subtle: the net has a real driver and is properly connected at the netlist level, but nothing downstream actually consumes the signal in a meaningful way — like a wire that's plugged in but runs to a dead outlet.
  24. 24 Why are multiply driven nets a hard structural concern?Beginner: Two active drivers fighting over one ordinary net is a real structural problem, not a style nitpick — they can demand different logic values on the same wire at the same time. That's exactly why a "multiple driver" message from the tool deserves immediate review rather than being waived through.
  25. 25 Why inspect constant-driven pins and nets?Beginner: A constant value (a pin permanently tied to logic 0 or logic 1) isn't automatically suspicious — some are completely intentional, like a mode-select strap that's hardwired for this particular chip variant or configuration. But a constant can *also* be evidence that something went wrong upstream — synthesis optimized away logic it thought was redundant, a clock got accidentally tied off, or an enable signal that should be dynamic got hardcoded because of a missing connection or a constraint bug.
  26. 26 Which logical counts should be reconciled?Beginner: Think of this as taking inventory after a shipment arrives — you're not re-verifying every connection, you're checking that the counts on the packing slip match what actually showed up. Compare ports, hierarchical cell instances, sequential cell counts, combinational cell counts, memory/macro counts, net counts, and unresolved reference counts against what the synthesis handoff reported.
  27. 27 Why inspect hierarchy before applying SDC?Beginner: SDC commands like `create_clock`, `set_input_delay`, or `set_false_path` all target objects by path — and those paths only exist if they match what ICC2 actually loaded, not what the RTL author originally wrote. Synthesis routinely renames, flattens, or removes hierarchy: a module boundary that existed in RTL might be gone after optimization, or an instance name might have picked up a synthesis-tool suffix.
  28. 28 Why can a syntactically valid SDC still be wrong?Beginner: Syntax just asks: does this command follow the language's grammar? Meaning asks something completely different: does it actually select the clocks, ports, pins, modes, and values you intended? A file can parse cleanly and still be functionally wrong — for example, a port name that changed during synthesis means the command runs without error but silently selects nothing.
  29. 29 What does an empty collection during SDC loading indicate?Beginner: An empty collection means your selector (something like `get_ports`, `get_cells`, `get_pins`) matched zero objects in the current design — the command didn't error, it just quietly found nothing. This is one of the most dangerous "silent failures" in SDC loading, because a constraint applied to an empty collection isn't an error — it just does nothing, and your design proceeds as if that constraint never existed.
  30. 30 What must be checked for a primary clock?Beginner: A primary clock originates at a real design source, typically an input port — it's not derived from any other clock in the design. Verification means checking its source object and name are correct, its period and waveform are as intended, and that it's visible in the right modes.
  31. 31 What is a virtual clock and why is it used?Beginner: A virtual clock is a timing reference that has no physical source anywhere inside your block — it's not an input port, not a generated clock off internal logic, nothing you can point to on the die. It exists purely to describe timing behavior happening outside the block boundary — commonly used to model an external device's launch or capture clock when you don't have (and don't need) that device's actual clock network inside your design.
  32. 32 What makes a generated clock different from a primary clock?Beginner: A primary clock is the true starting point of your timing reference — it begins at a real design source, usually an input port, and its period and waveform define the base time reference that everything downstream gets measured against. A generated clock, by contrast, doesn't originate independently — it's *derived* from a master clock through actual logic in your design, like a clock divider or a mode-select MUX, and its timing characteristics (period, phase, edges) come from that master-source relationship, not from a fresh, independent definition.
  33. 33 What do input and output delays describe?Beginner: Input and output delays describe time spent *outside* your block — everything happening before a signal reaches your input pin, or after it leaves your output pin, relative to a reference clock. They are explicitly not the delay of the block's own internal input receiver or output buffer — a common beginner mistake is thinking `set_output_delay` models the output driver's own speed, when really it models whatever sits downstream (the receiving device's setup/hold requirement plus any board/interconnect delay).
  34. 34 Why check driving cell, input transition, and output load?Beginner: These three settings define the electrical "weather" around a port — without them, the timing engine has no idea how fast a signal is realistically switching or how much it has to drive, so any delay number it calculates is essentially a guess. The driving cell (or an explicit `set_input_transition`) tells the tool how sharp or sluggish the incoming edge is — a slow input transition ripples forward and makes every downstream cell look artificially slower too.
  35. 35 What does check_timing check at this stage?Beginner: `check_timing` is not a timing-quality check (it doesn't report slack) — it's a setup/coverage health check that runs before you should trust any slack numbers at all. It looks specifically for missing or inconsistent timing intent: clock pins with no clock reaching them ("no-clock" points), output/register endpoints that never got constrained (unconstrained endpoints), timing loops (combinational cycles that break static analysis), and generated-clock definition problems (a derived clock missing its source or divide-by relationship).
  36. 36 What evidence is required before beginning floorplanning?Beginner: Being "ready" here isn't a feeling — it's a specific checklist: matched provenance (netlist/SDC revisions agree with the handoff record), resolved linking (no unexpected unresolved references), classified structural findings (undriven/unloaded/multi-driver nets reviewed and understood, not just silenced), applied and reviewed SDC, complete clock/I-O intent, confirmed active scenario coverage, and any waivers explicitly owned by someone. Every one of these should produce a concrete, named result — this clock exists with this period, this reference is resolved to this library cell — not a generic "looks fine."
  37. 37 What is a floorplan, and what problem does it solve?Beginner: A floorplan is the first step where a logically valid netlist gets turned into a physical plan — where boundaries, rows, macros, pins, and reserved channels actually live in physical space, obeying real technology and library rules. The best analogy is arranging rooms and hallways in a building before you furnish anything — except unlike a building sketch, every object here has to satisfy hard, mechanically-checkable rules (site grids, layer directions, spacing rules), not just aesthetic judgment.
  38. 38 How do die, core, and core offset differ?Beginner: Picture the die as the full piece of land you own, and the core as the buildable footprint inside it — the core is where your standard-cell rows and most of your implementation actually lives. The core offset is simply the gap between the die edge and the core edge on each side — and crucially, that gap doesn't have to be the same on all four sides.
  39. 39 Which area categories must be separated before calculating a floorplan?Beginner: Think of "total area" as a mixed bag of very different things — you can't compute a meaningful utilization number until you've sorted that bag into buckets. Separate at least these categories: standard-cell area, hard-macro area, fixed/physical-only cell area (taps, end-caps, corner cells), placeable area, reserved area, and whitespace.
  40. 40 What are whitespace and target utilisation?Beginner: Whitespace is the placeable area left over after your counted cells have been assigned their area — it's working room for optimization cells, routing access, and future ECOs, not automatically "wasted" silicon. Target utilization is just the planned fraction of placeable area you intend the explicitly counted objects to occupy — but that number is meaningless until you state exactly what's in the numerator and what's in the denominator.
  41. 41 How do you estimate required placeable area from target utilisation?Beginner: The formula is simple division, but the interpretation is where people trip up: required placeable area = counted cell area / target utilisation, not the other way around. Worked example: if your counted standard cells add up to 600,000 um^2 and you want them to occupy 60% of placeable area, you need 600,000 / 0.60 = 1,000,000 um^2 of placeable area total — not 600,000 um^2 with 60% left as margin.
  42. 42 How do target, effective, and local utilisation differ?Beginner: Target utilization is your input assumption going in; effective utilization is what actually got achieved after real exclusions (blockages, macros, halos) are accounted for; local utilization narrows the question to a specific smaller region instead of the whole block. These answer genuinely different questions, and comparing across them is meaningless unless you're using the same object classes, the same exclusions, and the same region definition each time.
  43. 43 What is core aspect ratio?Beginner: Aspect ratio is simply width divided by height of the core: AR = W / H. AR = 1 is a square core; AR = 2 means the core is twice as wide as it is tall. Two floorplans can have identical area but very different shapes — a 1000×1000 µm square and a 2000×500 µm rectangle have the same area (1,000,000 µm²) but wildly different aspect ratios, and that shape difference changes everything about routing and timing.
  44. 44 How do you derive rectangular core width and height from area and aspect ratio?Beginner: This is one of the most basic but most-used floorplanning calculations — you know how much area your logic needs, and you've decided (for I/O, package, or routing reasons) what shape you want that area to take, and you need actual width/height numbers to build a floorplan from. Define **aspect ratio (AR)** as width divided by height (`AR = width / height`) — an AR of 1.0 means a square, an AR of 2.0 means a rectangle twice as wide as it is tall, and an AR of 0.5 means twice as tall as wide.
  45. 45 How do asymmetric offsets change die dimensions?Beginner: Don't assume all four sides of the core-to-die offset are equal — in real floorplans they often aren't, because different sides reserve different amounts of space for I/O cells, power rings, bond pads, or keepout margins. The rule is additive per axis: die width = core width + (left offset + right offset); die height = core height + (bottom offset + top offset). You add the actual measured offset on each side, not a single "the" offset doubled.
  46. 46 How do sites, rows, and routing tracks differ?Beginner: These three answer three completely different questions, and mixing them up is a common beginner mistake: a site answers "where may a cell origin legally land," a row answers "where do standard cells actually get placed," and a routing track answers "where may a wire centerline run." A site is the smallest legal placement increment — think of it as the grid unit that every standard-cell origin must snap to.
  47. 47 Why do row orientation and fragments matter?Beginner: Think of standard-cell rows like bookshelves: every row has to sit in a legal orientation so a cell's power rail lines up with the row's VDD/VSS rail — flip a shelf the wrong way and books (cells) that need to sit on it simply can't. Rows commonly alternate orientation (R0/MX) from one row to the next specifically so adjacent rows can share a power rail by abutment, but that alternating pattern is a library/methodology choice, not a universal law — always check what the target library actually supports.
  48. 48 How does a hard macro differ from a standard cell during floorplanning?Beginner: A hard macro (think SRAM or a hardened IP block) arrives with its size, shape, and pin locations frozen — it's furniture, not something you can reshape to fit the room. A standard cell is tiny and numerous by comparison — thousands of interchangeable Lego bricks that get arranged later, inside whatever legal rows the macro layout leaves behind.
  49. 49 What should drive initial macro placement?Beginner: Macro placement isn't an aesthetic exercise — it should follow the actual dataflow: which macros talk to which, how critical that connection is, and where the I/O and clock/reset sources sit. Picture "fly lines" (rubber-band connectivity lines) stretched between macros and ports — a good placement is one where those lines are short and unobstructed, giving wires a direct, legal corridor instead of a scenic detour.
  50. 50 Why do macro orientation and alignment matter?Beginner: Rotating a macro is like turning a cabinet around — it changes which side its doors open on, and for a macro, the "doors" are its signal and power pins. A rotation can be perfectly legal geometrically (it fits the footprint) while still pointing pins away from the logic that needs them, or misaligning power pins from the strap grid they're meant to land on.
  51. 51 What makes a macro channel usable?Beginner: White space between macros looks like "free routing room" on screen, but it's only usable if it actually has enough width and geometry for signal tracks, facing pins, power straps, vias, shielding, and buffers — visible space and routable space are not the same thing. Different spacing rules apply to macro-to-macro gaps, macro-to-boundary gaps, and macro-to-standard-cell gaps — treating them as one generic "keep-out" number will misjudge channel capacity.
  52. 52 How does a macro halo differ from a placement blockage?Beginner: A halo (keepout margin) is attached to a macro — like a personal-space bubble — so wherever the macro moves, the halo moves with it automatically. A placement blockage is a fixed rectangle drawn on the floorplan itself; it doesn't care what's placed nearby and it stays put even if every macro around it shifts.
  53. 53 What are boundary, end-cap, and corner cells?Beginner: Core boundary cells sit at the ends of standard-cell rows — their job is to protect and properly terminate the row edge (well, diffusion, etc.) so the row doesn't end with an invalid or DRC-violating structure. Inside/outside corner cells handle the actual corners of the core or of a voltage area — an outside corner (convex, like a normal rectangle's corner) and an inside corner (concave, like the corner of an L-shaped notch) need different cells because the geometry they're closing off is different.
  54. 54 How do chip I/O, top-level ports, macro pins, and block pins differ?Beginner: These are all "connection points," but they live at very different physical and logical boundaries, and confusing them is a common source of miscommunication between floorplan, package, and RTL teams. Chip I/O (pads or bumps) are where the die physically connects to the package — their placement and rules are driven by packaging constraints (bond-wire pitch, bump grid), not by what's convenient for internal routing.
  55. 55 What is a feedthrough?Beginner: A feedthrough is a signal that enters a block, passes through it, and leaves again without ever actually being used by that block's own logic — it's just borrowing the block as a physical hallway to get somewhere else. The upside is real: routing a signal through a block can be a shortcut compared to detouring all the way around it at the top level, which can shorten wire length and improve timing for that top-level path.
  56. 56 What does early congestion mean?Beginner: Early congestion estimation is a rough, pre-route sanity check: it compares how much routing *demand* (nets that need to cross a region) exists against how much routing *capacity* (actual track resources) is available, in coarse rectangular regions across the chip. The clearest analogy is a highway system: the average traffic flow across the whole city can look totally fine while one specific junction is completely gridlocked — congestion is fundamentally a **local** phenomenon, and averaging it away at the chip level hides the real problem.
  57. 57 What is the difference between a legal pin and an accessible pin?Beginner: A "legal" pin just means it obeys placement rules — it's sitting somewhere the DRC deck allows. An "accessible" pin is a stronger claim: there's actually a usable route to it, on a permitted layer and track, with nothing in the way. It's the difference between a door drawn correctly on a blueprint and a door you can actually walk through — furniture (blockages, stacked shapes, neighboring PG shapes) can block a perfectly legal door.
  58. 58 Why reserve power-grid resources during floorplanning?Beginner: Power rings, straps, rails, and their vias aren't free — they consume real area and real routing tracks, on the same "roads" signal wires want to use. If you plan signal channels or pin access before reserving power's footprint, you'll end up designing corridors that power later claims out from under you — so PG corridors have to be reserved early, before signal planning locks in.
  59. 59 How does a power domain differ from a voltage area?Beginner: A power domain is a logical concept — it says which electrical rules (supply, isolation, retention) apply to a group of cells. A voltage area is the physical fence — it says where on the floorplan those cells are actually allowed to sit. They're related but not synonyms: you can define a power domain in UPF and still get the physical implementation wrong if the voltage area's shape, alignment, or utilization doesn't actually support it.
  60. 60 How can a floorplan affect timing before placement is complete?Beginner: Even before a single standard cell is placed, the floorplan is already shaping how long wires will eventually have to be — and wire length translates almost directly into estimated interconnect delay. Physical distance matters most obviously: two logically connected blocks placed far apart on the die will need longer wires than the same two blocks placed close together, even though the logic connecting them hasn't changed at all.
  61. 61 What evidence makes an initial floorplan reviewable?Beginner: A screenshot of a floorplan tells you what it looks like, not whether it's actually sound — real reviewability comes from reports and saved constraints that show what the *tool* actually understands, not what the picture visually suggests. A reviewable floorplan has to demonstrate, with evidence: deliberate (not accidental) boundaries, a stated utilization number, genuinely usable rows, macro locations with a justification (not just "it fit there"), feasible routing channels, properly constrained pins, early congestion/timing evidence, reserved PG resources, voltage-area legality, and — critically — reproducible write-out (someone else can regenerate your evidence from the same inputs).
  62. 62 What is standard cell placement, and what are its primary goals?Beginner: Placement is the step that turns an abstract netlist ("this gate connects to that gate") into real geometry — every standard cell gets an exact (X, Y) coordinate and a legal row orientation. It's optimizing three things at once, and they pull against each other: total wirelength (measured cheaply via HPWL), timing slack under an idealized zero-skew clock, and routability — keeping local congestion from spiking anywhere.
  63. 63 What are the four fundamental stages of the placement flow?Beginner: Production placement isn't one monolithic step — it runs as four distinct, purpose-built phases, and knowing which phase you're in tells you what kind of problem you're actually debugging. **Global Placement** comes first: an analytical engine treats the whole core as continuous space and spreads cells around to minimize estimated wirelength (typically half-perimeter wirelength) while avoiding density spikes. Cell coordinates here are still non-integer floats, and cells can still overlap — this stage is about rough positioning, not legality.
  64. 64 What are Tie Cells (TIEHI / TIELO), and why are direct connections to VDD/VSS prohibited?Beginner: Tie cells give a gate a clean, high-impedance logic-1 or logic-0 reference instead of letting a designer wire an input straight to the VDD or VSS rail — that direct wiring is actually dangerous, not just sloppy. Power rails aren't perfectly quiet: switching transients create inductive voltage spikes (L·di/dt), and a direct tie exposes the transistor's ultra-thin gate oxide to those spikes, which can literally punch a hole through it.
  65. 65 What are Well-Tap cells, and how do they prevent CMOS latchup?Beginner: Every bulk-CMOS standard cell secretly contains a parasitic four-layer PNPN structure — basically an accidental thyristor sitting between VDD, the N-well, the P-substrate, and VSS. If substrate current builds up (from noise, I/O undershoot, or a fast transient) and the resulting I·R drop across the well/substrate resistance crosses about 0.7 V, that parasitic thyristor turns on and regeneratively shorts VDD straight to VSS — that's latchup, and it can physically destroy the die.
  66. 66 What are Endcap and Boundary cells, and where are they inserted?Beginner: Standard cells depend on continuous N-well, substrate, and poly geometry running the length of a row — an abrupt dead-end at the row's edge isn't just untidy, it's a manufacturing hazard. At an open row end, lithography sees a sudden transition from patterned silicon to empty space, and that optical discontinuity distorts nearby polysilicon gate shapes during exposure — endcap cells absorb that distortion so real logic cells don't take the hit.
  67. 67 What is Half-Perimeter Wire Length (HPWL), and why is it used in Global Placement?Beginner: HPWL is the cheapest useful stand-in for "how long will this net's wiring be": draw the smallest bounding box around all the net's pins, and HPWL is just (width + height) of that box. It's fast for a reason — global placement has to evaluate millions of candidate cell moves per second, and there's no time to run real routing on each trial, so HPWL gives an O(N) estimate instead.
  68. 68 What is the difference between Core Utilization and Local Placement Density?Beginner: Core utilization is a single chip-wide number — total cell area (standard cells plus macros) divided by total core area — and it's typically targeted around 65–75% for modern digital blocks as a static planning goal. Local placement density is a much more local, moving-window measurement: cell area inside one G-cell tile divided by that tile's area — and it can spike to 90–98% in one pocket even while 40% of the die sits completely empty.
  69. 69 What is Placement Cell Padding, and how does it relieve routing congestion?Beginner: Complex standard cells — AOI22s, OAI33s, wide MUXes, scan flops — pack a lot of pins into a small footprint, and when several of them abut directly, their combined pin demand can exceed what the local metal layers can route, causing shorts. Padding is a placement-time trick: tell the tool to treat a cell as wider than it physically is (e.g., a 4-site cell padded to look 6 sites wide), reserving empty "halo" sites on either side that no other cell may occupy.
  70. 70 What is Magnet Placement, and how is it used during physical implementation?Beginner: Magnet placement is exactly what it sounds like: you designate a fixed object — an I/O port, a macro, or even one macro pin — as a "magnet," and the placer applies an attractive pull to every standard cell directly wired to it. Without this, interface registers connected to a fixed off-block port can end up scattered randomly across the core by unconstrained global placement, which then makes closing the interface's input-delay timing painful.
  71. 71 What are Spare Cells, and why must they be distributed uniformly pre-CTS?Beginner: Spare cells are unconnected, uncommitted logic gates dropped into the die before CTS, purely as insurance — if a functional bug turns up after tapeout, you may be able to fix it without a full new mask set. A brand-new mask set costs millions and takes months; if spare gates already exist on silicon nearby, the fix can sometimes be done with just a metal-and-via change, which is roughly 5–10x cheaper and 3x faster.
  72. 72 How do clock skew, latency, jitter, and uncertainty actually differ, and how do they combine?Beginner: Skew is a spatial difference: the gap in clock arrival time at two different leaf registers at the same moment. Jitter is a temporal difference: how much a clock edge's timing varies at one single point across cycles. Latency is how long the clock takes to arrive at all, split into source latency (before the clock enters the network) and network latency (through the distribution tree to the sink). Uncertainty is the combination CTS actually has to budget for -- skew plus jitter together -- because both eat into the same setup/hold margin even though they come from different physical causes.
  73. 73 How does CTS group leaf registers before it starts inserting buffers?Beginner: CTS first identifies leaf sink points (non-clock pins of standard cells not defined as clock ports) and groups nearby ones into a virtual cluster; leaf cells far from any cluster get moved to the nearest one. Once clusters and locations are set, buffer insertion proceeds so propagation delay is equal to each cluster and skew inside each cluster is minimized. Smaller clusters mean less skew but more buffering levels, which raises total insertion delay -- a real tradeoff, not a free choice.
  74. 74 What design rule constraints does CTS actually have to meet, separate from timing?Beginner: CTS has its own DRC set, independent of setup/hold: max transition, a skew requirement, max capacitance, and max fanout. These aren't optional nice-to-haves -- a clock tree that meets setup and hold perfectly but violates max transition on a clock net is still a broken tree, because electrical DRC violations are checked and reported separately from timing violations.
  75. 75 Why does clock distribution get so much attention in power closure specifically?Beginner: The clock distribution network accounts for 30% or more of total dynamic power in modern ASICs -- some sources put it at 30-40% of total chip power -- because clock nets switch at the highest frequency in the design and carry considerable capacitive loading. An optimum clock tree matters for both performance and power, and clock gating substantially reduces this cost.
  76. 76 What is a multisource clock tree, and why would a design need one instead of a traditional CTS-built tree?Beginner: A multisource clock tree (MSCTS) is a custom clock structure with more on-chip-variation tolerance and better cross-corner performance than a traditional tree. It consists of a global clock structure (root, global tree -- usually an H-tree -- mesh drivers, and the clock mesh) plus local subtrees driven either by predefined tap drivers (a regular MSCTS) or directly from multiple mesh points (a structural MSCTS).
  77. 77 What does report_clock_qor actually show you, and what do its -type variants each report?Beginner: report_clock_qor is the summary command for clock tree quality: latency, skew, DRC violations, area, and buffer count in its default form. The -type option narrows it: -type latency for longest/shortest path, -type drc_violators for max transition/capacitance violators, -type robustness for cross-corner ratio, -type balance_groups for interclock balance QoR, -type local_skew for worst local skew per group, and -type power for per-clock power breakdown.
  78. 78 Why does CTS have to wait until after placement instead of running earlier in the flow?Beginner: CTS needs real physical locations for every leaf register to build a tree that actually balances delay to each one -- before placement, those locations don't exist yet. Running CTS on an unplaced or partially-placed design would mean building a tree around positions that are about to change, making the whole tree invalid the moment placement moves anything.
  79. 79 How are clock tree DRC constraints different from clock tree timing constraints, and why does CTS need both?Beginner: Timing constraints (setup/hold via skew and latency) ask whether the clock arrives at the right time at every register. DRC constraints (max transition, max capacitance, max fanout) ask whether every individual clock net is electrically sound, independent of when it arrives. A tree can be timing-clean and DRC-broken, or DRC-clean and timing-broken -- they're genuinely separate axes CTS has to satisfy simultaneously.
  80. 80 When does CTS actually split a clock cell, and how can you tell a split cell apart from the original?Beginner: split_clock_cells splits a clock cell to fix a DRC violation by dividing its load between two cells. A cell is NOT split if it has no DRC violations, has dont_touch/size_only/fixed placement, or would require punching a new port on a frozen power domain or block boundary. New cells are named <original_cell_name>_split_<integer>, and settings/constraints are copied from the original.
  81. 81 Are "clock-gating cell" and "ICG" the same thing, or is there a real distinction?Beginner: In practice they refer to the same physical cell -- a clock-gating cell (CGC) is what gets called an integrated clock gate (ICG) once it's placed in the tree and merging/optimization options (merge_clock_gates, cts.icg.merge_cross_level, optimize_icgs) act on it. The terms aren't describing two different components; CGC is the general term and ICG is the specific instance type the flow's options operate on.
  82. 82 What is a clock mesh driver, and how is it different from a tap driver?Beginner: A mesh driver feeds the clock mesh itself -- the 2D grid of horizontal and vertical straps joined by vias at intersections -- and is inserted via create_clock_drivers with -short_outputs to tie all driver outputs together for the mesh. A tap driver is different: it's what feeds a local subtree off the mesh in a regular multisource clock tree, connected to the mesh but driving downstream logic, not the mesh grid itself.
  83. 83 How would you export or visualize clock tree QoR data instead of just reading a text report?Beginner: report_clock_qor supports -csv with -output <file> to export the report as CSV for spreadsheet analysis, and -histogram_type latency|transition|capacitance|local_skew|robustness|wire_delay_fraction to get a distribution view instead of a flat table -- useful for spotting outliers across hundreds of leaf sinks that a table alone would bury.
  84. 84 Beyond setup and hold, what other timing checks does STA run at a sequential element?Beginner: STA runs several distinct check types at sequential boundaries: setup and hold (data stability before/after the clock edge), removal (minimum time between a clock edge and releasing an async control signal like reset), recovery (minimum time between releasing that signal and the next clock edge), period (minimum time for one full clock cycle), and minimum pulse width high/low (MPH/MPL). Each protects a different failure mode -- removal and recovery specifically guard asynchronous reset/set behavior, not the synchronous data path.
  85. 85 What do MPH and MPL checks actually verify, and where else does MPL-style logic show up?Beginner: MPH (Minimum Pulse Width High) verifies a clock's positive pulse stays high long enough; MPL (Minimum Pulse Width Low) verifies the negative pulse stays low long enough. The same underlying MPL-style logic is also used for transparent-latch setup/hold slack adjustments -- a latch's transparent window has to stay open long enough for data to actually pass through it, which is structurally the same "minimum duration" problem as a clock pulse.
  86. 86 What actually happens when a flip-flop's setup or hold time is violated, and what's the standard fix?Beginner: Violating setup or hold can drive a flip-flop into a metastable state, where the output settles to an intermediate value and may never resolve to a clean 0 or 1 in time. The standard mitigation is double synchronization -- passing the signal through two or more flip-flops in series, giving the metastable state extra clock cycles to resolve before it's used by downstream logic.
  87. 87 What are the four standard timing path types STA classifies paths into, and why does that classification matter?Beginner: The four path types are input-to-register (I2R), register-to-register (R2R), register-to-output (R2O), and input-to-output (I2O) -- the standard 4-way STA path group classification. This classification matters because different path types often need different constraint treatment (I/O delays for boundary paths, clock relationships for R2R paths) and different optimization priority during timing closure.
  88. 88 What's the practical difference between timing with a wire-load model and timing with real layout data?Beginner: A zero wire-load model means pre-layout, zero net delays -- cell propagation delays only, useful early but unrealistic. A real wire-load model estimates loading/delay effect of fanout from the technology library (an area-based default) -- better than zero, still an estimate. Post-layout extracted-parasitics STA, using actual LEF/routing data, is far more accurate and meaningfully reduces timing closure surprises later in the flow.
  89. 89 What's the practical fanout guideline STA uses, and what does it actually control?Beginner: The rule of thumb: max fanout is typically 10 -- any net should drive a load equivalent to no more than 10 input cells. This is used to map the correct drive-strength cell against the stated fanout -- a driver sized for 10 loads won't perform correctly (transition, delay) if the design actually connects 20 loads to it.
  90. 90 Does ICC2's DRC checking actually enforce max fanout the same way it enforces max capacitance and max transition?Beginner: No -- this is a specific, important exception: max fanout DRC is NOT honored by ICC2 as a hard design rule constraint. Instead, opt.common.max_fanout is a soft optimization constraint. Min capacitance, max capacitance, and max transition DO have technology-specific defaults in the logic libraries and can be overridden as real DRC -- max fanout is handled differently.
  91. 91 What's the actual difference between a cluster and a region as global placement grouping mechanisms?Beginner: A cluster is a group of cells placed near each other, with location undefined until placement completes -- rarely used now that interconnect-driven placement matured. A region is similar but its location is defined BEFORE placement -- a soft region is a physical constraint with a boundary that may still change during placement; a hard region has boundaries cells cannot cross. Regions are further exclusive (only assigned cells allowed) or non-exclusive.
  92. 92 What's the practical target fanout range for a high-fanout net driver, and why does HFN synthesis need its own handling at all?Beginner: High-fanout nets (like reset or chip-enable) have one source driving many cells across the core -- not timing-critical individually, but strongly impacting routing area. The reasonable target: reduce fanout to between 40 and 50 connections per driving cell, via buffer insertion (high-fanout net synthesis). Without this, one driver trying to reach hundreds of loads directly would create a routing and drive-strength problem the tool has to solve some other way.
  93. 93 Why does a long wire with low fanout still need special handling during placement optimization?Beginner: A long wire (small fanout, but driver far from receiver) is often the result of the receiver having stronger connectivity to other instances than to its actual driver. Being highly resistive, it causes a large input transition at the receiver, which increases receiver propagation delay. The fix: segment long wires with buffers -- the same underlying principle as clock buffer insertion, applied to a data-path net.
  94. 94 What's the practical difference between marking a cell dont_touch and marking it size_only?Beginner: set_dont_touch excludes a cell from optimization entirely -- nothing about it changes. set_size_only allows sizing (swapping to a different drive-strength variant) but nothing else -- the cell stays in place, keeps its function, but can still be resized to help timing. dont_touch is the stronger, more restrictive constraint; size_only is a middle ground that still gives the optimizer one lever to use.
  95. 95 What does set_auto_disable_drc_nets actually let you turn off, and why would you ever want to disable DRC on a net category?Beginner: set_auto_disable_drc_nets controls DRC checking on specific net categories: -none re-enables DRC for all nets, -all disables DRC on all clock/constant/scan-enable/scan-clock nets, and individual flags (-constant, -on_clock_network, -scan) let you target just one category. This exists because some net categories (e.g. constant-tied nets) genuinely don't need the same electrical DRC scrutiny as functional data nets, and checking them anyway wastes analysis effort or produces noise.
  96. 96 What does set_dont_touch_network actually protect by default, and how does -clock_only narrow that scope?Beginner: By default, set_dont_touch_network [get_clocks CLK] protects BOTH clock paths AND clock-as-data paths -- meaning a clock signal used somewhere as an ordinary data input is also protected. -clock_only narrows that to just the clock paths, leaving clock-as-data usage open to optimization. -clear removes the protection entirely.
  97. 97 What's the difference between legalize_placement and refine_placement -- do they do the same kind of work?Beginner: legalize_placement removes cell overlap and fits the placement into the row structure, correcting illegal positions to legal ones -- a correctness operation. refine_placement is incremental placement specifically to minimize congestion (with an -effort level, default medium) -- a quality-improvement operation on an already-legal placement. They're not interchangeable: legalization fixes illegality, refinement improves an already-legal result.
  98. 98 What does routing do, and where does it sit in the PnR flow?Beginner: Routing turns every logical connection into real metal. Before this stage a net is only an estimate, a straight or Steiner line the tools use to guess wire length and delay. The router replaces that guess with wires on real layers, joined by vias, that obey every width and spacing rule in the technology file.
  99. 99 What must be true before you start routing?Beginner: The block has to be routable and roughly timing-clean before the router touches it. That means power and ground already routed, clocks built and propagated, estimated congestion acceptable, estimated timing close to zero slack, no max capacitance or transition violations, and a clean `check_routability`. Zroute also needs every design rule defined in the technology file, because that is the only place it reads rules from.
  100. 100 What is the difference between global routing and detail routing?Beginner: Global routing decides which regions a net passes through; detail routing decides exactly which tracks, layers and vias it uses. Global routing works on a coarse grid of global routing cells (GCells) and never draws real geometry. Detail routing draws the actual metal on tracks and cleans up every design rule violation.
  101. 101 What are Zroute's engines, and which command drives each?Beginner: Zroute, the ICC2 router, has five engines: global routing, track assignment, detail routing, ECO routing and routing verification. The first three can be run one at a time with `route_global`, `route_track` and `route_detail`, or all together with `route_auto`. ECO routing and verification are only reached through their own task commands, `route_eco` and `check_routes`.
  102. 102 When would you run route_global, route_track and route_detail separately instead of route_auto?Beginner: Run the steps separately when you want to look at the result of global routing before paying for detail routing. `route_auto` runs all three engines back to back, which is fine on a stable block. On a new or congested block, stopping after `route_global` lets you read the congestion map and fix a hot spot in minutes instead of discovering it hours later as thousands of DRCs.
  103. 103 What is a GCell, and how is its routing capacity calculated?Beginner: A GCell (global routing cell, or GRC) is one tile of the coarse grid the global router works on. Its capacity is how many nets can cross it in one direction, which comes from how many tracks fit: the number of layers running that way times the cell size divided by the track pitch. The router compares demand against that capacity in every GCell to decide where congestion is.
  104. 104 What does overflow mean in a congestion report?Beginner: Overflow is how many more nets want to cross a GCell edge than there are tracks to carry them. If 14 nets want to cross and only 11 tracks exist, the overflow is 3. `report_congestion` adds overflow up across layers, and it ignores underflow, so a spare layer does not hide a crowded one.
  105. 105 What is preferred routing direction, and why do layers alternate?Beginner: Each metal layer has a preferred direction, horizontal or vertical, and the router keeps most wires on that layer running that way. Adjacent layers alternate direction so a horizontal wire on one layer never blocks a vertical wire on the next; they cross using a via. Wrong-way segments are legal but expensive, because they block tracks that other nets need.
  106. 106 How do routing tracks relate to pitch, and why must pins be on-grid?Beginner: Tracks are the lines a gridded router places wires on, laid out at the layer pitch, which is minimum width plus minimum spacing. A wire drawn on a track automatically keeps legal spacing from wires on the neighbouring tracks. A pin that does not line up with the track grid forces the router to jog off-grid, and those connections produce DRCs that are very hard to clean up.
  107. 107 How and why do you set min and max routing layers?Beginner: Min and max routing layers set the band of metal that signal nets are allowed to use. M1 is usually kept for standard cell pins and the top layers for power and top-level routing, so the block routes in the layers between. Set them with `set_ignored_layers` before placement, because RC estimation and congestion analysis use them as well as the router.
  108. 108 What is a via, and why does via count matter?Beginner: A via is the vertical connection between two metal layers: a small cut through the insulator, with metal enclosure around the cut on both the layer below and the layer above. Every layer change in a route needs one. Via count matters because each via adds resistance, often more than the wire around it, and each single-cut via is a yield and reliability risk.
  109. 109 What is a redundant (double) via, and why insert it?Beginner: A redundant via adds a second cut next to an existing single cut, so the connection survives if one cut fails. The two cuts also share current, which lowers via resistance and improves electromigration margin. Success is measured by the redundant via conversion rate, the percentage of single vias that were converted.
  110. 110 What does track assignment do between global and detail routing?Beginner: Track assignment takes each global route, which only says which GCells a net passes through, and places its long segments on real tracks. It does this across whole rows and columns of the block at once, so parallel nets are spread sensibly before detail routing starts. After it finishes, every net is drawn in metal, but there are still many violations near pins for detail routing to fix.
  111. 111 What is search-and-repair in detail routing?Beginner: Search-and-repair is the part of detail routing that clears design rule violations. The router first connects every net, even if that leaves shorts and spacing errors. It then runs repeated iterations that search for violations, rip up the wires involved in a small area, and reroute them until the violations are gone or stop improving.
  112. 112 What are the common routing DRC violations?Beginner: The ones you see most are different-net spacing, shorts, minimum area, minimum width and length, end-of-line spacing, via enclosure problems, and open nets. `check_routes` lists them by type and saves the DRCs to the `zroute.err` error data; open nets appear in its text report. Knowing which type dominates tells you where to look for the cause.
  113. 113 What is the difference between an open and a short after routing?Beginner: An open is a pin that is not connected to the rest of its net, so the signal never arrives. A short is two different nets touching in the layout, so the silicon merges signals that the netlist says are separate. Both are hard failures that must be zero at signoff, and neither shows up reliably in timing reports.
  114. 114 What does check_routes catch that check_lvs doesn't, and vice versa?Beginner: `check_routes` is the router's verification check: it looks for DRCs, open nets, antenna violations and voltage area violations on routed signal nets. `check_lvs` is a connectivity check across signal, clock and power and ground nets that looks for shorts, opens and floating shapes. They overlap on opens and shorts, but each covers things the other does not.
  115. 115 What is the antenna effect?Beginner: The antenna effect is damage to a transistor's gate oxide during manufacturing, not during operation. While the chip is being built layer by layer, a long wire connected only to a gate collects electrical charge from the plasma etch steps. With no driver connected yet to drain that charge away, it can discharge through the thin gate oxide and damage it permanently.
  116. 116 How are antenna violations fixed?Beginner: There are two main fixes: layer hopping and diode insertion. Layer hopping breaks a long wire with a short jump to another layer near the gate, so less metal is attached to the gate during the risky etch step; Zroute prefers this by default. Diode insertion adds a protection diode that gives the collected charge a safe path to the substrate.
  117. 117 What is crosstalk, and what are aggressor and victim nets?Beginner: Crosstalk is unwanted coupling between two wires that run next to each other. When one wire, the aggressor, switches quickly, the coupling capacitance between them pushes a small voltage onto its neighbour, the victim. If the victim is quiet, that shows up as a glitch; if the victim is also switching, it changes the victim's delay.
  118. 118 What is net shielding, and what does it cost?Beginner: Shielding places power or ground wires on both sides of a sensitive net, usually a clock, so no switching signal runs directly next to it. That removes almost all coupling from neighbouring signals. The cost is routing tracks, since one net now takes about three, and extra sidewall capacitance to the shields, which slows the shielded net.
  119. 119 What is a non-default routing rule (NDR)?Beginner: A non-default routing rule (NDR) is a stricter set of width and spacing rules, and optionally specific vias, that you assign to chosen nets instead of the technology defaults. It is typically used on clocks and other critical nets: a wider wire lowers resistance and extra spacing lowers coupling. Width rules in an NDR are hard constraints and apply to via enclosures too.
  120. 120 Why are clock nets routed before signal nets?Beginner: Clocks are routed first so they get clean routing resources, their NDRs and any shielding, before thousands of signal nets fill the tracks. CTS balanced the tree assuming certain wire lengths and layers; routing the clocks first keeps that intact. If signal nets went first, clocks would be forced into detours that change skew and latency.
  121. 121 What is a routing blockage, and when do you use one?Beginner: A routing blockage is a region where routing is not allowed on the layers you name. Zroute treats it as a hard rule, so wires detour around it. You use one to keep routing off sensitive areas, away from macro pins or edges that cause DRCs, or to reserve space, and you add `-zero_spacing` when the goal is to keep vias out.
  122. 122 What is parasitic extraction, and why is it redone after routing?Beginner: Parasitic extraction calculates the resistance and capacitance of every routed net from its real geometry. Those values, usually written as SPEF, feed timing and signal integrity analysis. Before routing they are estimates; after routing they come from actual wire length, width, layers, vias and neighbours, so they have to be recalculated.
  123. 123 What sets a wire's resistance and capacitance?Beginner: Resistance grows with length and falls with width and thickness. Capacitance depends on how much surface faces other metal and how close it is: long, tall, closely spaced wires have the most. For routing decisions the practical rules are simple: wider wires lower resistance, more spacing lowers coupling, and fewer vias lower resistance further.
  124. 124 Why does timing change after routing even if placement didn't change?Beginner: Before routing, net delays come from estimates: virtual routes or global routes and estimated parasitics. After routing, every net has its real length, layers and vias, and real neighbours that add coupling. Those differences change delay, and crosstalk appears for the first time, so slack moves even though no cell moved.
  125. 125 What does postroute optimization (route_opt) do?Beginner: `route_opt` fixes timing and logical design rule violations after routing, using real parasitics. It extracts, updates timing, then optimizes setup, hold, area and logical DRCs such as transition and capacitance, typically by sizing and buffering cells. It then legalizes the changed cells and ECO routes to connect the changed nets and clear DRCs, which can also touch neighbouring wires.
  126. 126 How do you read routing statistics after detail routing?Beginner: Look at three things: wire length per layer, the split between horizontal and vertical wiring, and via statistics including the double via rate. `report_design -routing` gives shape counts, wire length and via statistics, and `report_wirelength` gives length per layer and direction. Together they tell you whether the router used layers sensibly and how much yield protection the vias have.
  127. 127 What must be clean before a routed block leaves the routing stage?Beginner: Connectivity has to be perfect: zero opens and zero shorts. DRC and antenna violations have to be zero or individually reviewed and accepted. Timing, transition, capacitance and signal integrity have to pass on routed parasitics in every active scenario, and the block has to be saved with the reports that prove it.
  128. 128 What is timing closure, and when is a design actually "closed"?Beginner: Timing closure is the loop of implementing, extracting, analyzing and fixing until every timing check passes in every scenario that matters. A design is closed when setup and hold both show WNS of zero or better and TNS of zero in every active scenario, the design rule checks are clean, and signal integrity has been included. That result has to come from PrimeTime on extracted parasitics, with analysis coverage checked so you know nothing was left untested.
  129. 129 What are WNS, TNS and the number of violating endpoints, and what does each tell you?Beginner: WNS is the worst negative slack, the single worst endpoint. TNS is the total negative slack, the sum of the negative slacks of all failing endpoints. NVE is the number of violating endpoints. Together they tell you how bad the worst path is, how much total work is left, and whether the problem is a few paths or a wide spread.
  130. 130 How is setup slack calculated from arrival and required time?Beginner: Setup slack is the required time minus the arrival time. Arrival time is when data actually reaches the capture flop, starting from the launch clock edge. Required time is the capture clock edge minus the setup time and uncertainty. Positive slack means the data arrives with time to spare; negative slack means it arrives too late.
  131. 131 How do you read a timing report line by line?Beginner: Read a timing report top to bottom in four blocks: the header, the launch side, the capture side and the slack line. The header names the startpoint, endpoint, path group and path type. The launch side builds data arrival time and the capture side builds data required time. The last line subtracts one from the other.
  132. 132 What typically causes a setup violation?Beginner: A setup violation means data reaches the capture flop too late for the next clock edge. The usual causes are too much logic between flops, weak drivers, long or detoured wires, a capture clock that arrives earlier than the launch clock, derates, and crosstalk that slows the signal. Most real failures are two or three of these adding together.
  133. 133 What causes a hold violation, and why can't slowing the clock fix it?Beginner: A hold violation means new data reaches the capture flop too soon after the clock edge, before the flop has safely stored the old value. It is caused by short data paths, a capture clock that arrives later than the launch clock, and fast process corners. Slowing the clock does not help because the hold check compares launch and capture on the same clock edge, so the period is not part of the equation.
  134. 134 Why do setup and hold fixes pull in opposite directions?Beginner: Setup wants data to arrive earlier and hold wants it to arrive later, so any change to a data path helps one check and costs margin on the other. Clock skew has the same effect: a later capture clock helps setup and hurts hold on the same flop. The goal is to fix each on the paths where the other has spare margin.
  135. 135 What are DRVs (max transition, capacitance, fanout), and why are they fixed before timing?Beginner: DRVs are design rule violations: a net whose transition time, load capacitance or fanout exceeds the limit set by the library or the constraints. They are fixed before timing because DRV fixing changes cells and buffers, which changes timing, and because timing on a violating net comes from outside the library characterized range. In PrimeTime, DRC fixing has the highest priority and can degrade setup or hold, so it runs first.
  136. 136 How are max-transition violations fixed?Beginner: A max-transition violation is fixed by making the driver stronger or the load it sees smaller. The three standard moves are upsizing the driver, inserting a buffer to break a long net, and splitting a large fanout across several buffers. PrimeTime can do this automatically with `fix_eco_drc` (PT), and ICC2 has `size_cell` (ICC2) and `add_buffer` (ICC2) for manual fixes.
  137. 137 How are max-capacitance violations fixed, and why do they matter beyond timing?Beginner: A max-capacitance violation means a driver sees more total load than its library limit. It matters beyond timing because the library was only characterized up to that load, and heavy load means higher current through the driver and its output wire, which is an electromigration and power concern. The fixes are to upsize the driver or split the load across buffers.
  138. 138 How does upsizing a cell fix setup, and what does it cost?Beginner: Upsizing replaces a cell with a stronger version of the same function, which drives its load faster and cuts delay. The cost is a larger input capacitance, which slows the stage before it, plus more area and leakage. It is the first fix PrimeTime tries for setup: by default `fix_eco_timing -type setup` (PT) uses cell sizing alone.
  139. 139 What is a threshold-voltage (Vt) swap?Beginner: A Vt swap replaces a cell with the same function, size and footprint but a different threshold voltage. Lower Vt cells switch faster and leak more, higher Vt cells are slower and leak less. You swap to LVT only on paths that need the speed, and swap non-critical cells to HVT to recover leakage.
  140. 140 When does adding a buffer make a path faster?Beginner: A buffer speeds up a path when the wire it breaks is long enough that its RC delay is larger than the buffer delay added. Wire delay grows roughly with the square of length, because both resistance and capacitance grow with length. Splitting the wire into shorter segments makes total delay grow roughly linearly. On a short wire, a buffer only adds delay.
  141. 141 How are hold violations fixed with delay cells, and where should they go?Beginner: Hold violations are fixed by adding delay to the data path so new data arrives after the hold window closes. The delay cell goes near the capture flop, on the branch that only the hold-failing endpoint uses. That keeps the delay off shared logic that may feed setup-critical endpoints. Always check the setup margin of the fixed path at the slow corner.
  142. 142 What is useful skew?Beginner: Useful skew is clock skew added on purpose to fix timing. Delaying the capture clock of a failing flop gives its incoming path more time, and takes the same amount from the path leaving that flop. It works when the next stage has spare slack to lend. ICC2 does this automatically with concurrent clock and data optimization.
  143. 143 Why split timing into path groups, and how do you read per-group results?Beginner: Path groups split a block's timing into buckets so one bad bucket cannot hide the others. By default each clock gets a group, and you add your own with `group_path` (SDC), commonly reg2reg, in2reg, reg2out and in2out. Read WNS, TNS and the violating-path count per group, because each group points at a different owner and fix.
  144. 144 Why isn't fixing the single worst path enough?Beginner: The worst path is only the first line of a long list. Behind it there are usually many paths within a few picoseconds, and they often share cells with it, so fixing one path leaves the rest failing or moves the problem to the next endpoint. You need the slack distribution and a report that covers every violating endpoint, not only the top path.
  145. 145 What is an ECO in physical design?Beginner: An ECO, or engineering change order, is a small, controlled change to a design that is already placed and routed, made instead of running the flow again. You edit the netlist, place only the changed cells, reroute only the affected nets and re-check. Timing ECOs fix timing or design rule violations, while functional ECOs change the logic itself.
  146. 146 What's the difference between a timing ECO and a functional ECO?Beginner: A timing ECO changes how fast the logic is without changing what it computes: sizing, Vt swaps, buffers and hold delay cells. A functional ECO changes what the logic computes, usually to match a corrected RTL. That difference decides where the change comes from, what equivalence is checked against and how much risk the change carries.
  147. 147 What is the PrimeTime ↔ ICC2 ECO loop?Beginner: The ECO loop splits the job between the tool that signs off timing and the tool that owns the layout. PrimeTime finds and fixes violations with signoff parasitics and writes the edits with `write_changes` (PT); ICC2 sources that script, places the new or resized cells and reroutes the touched nets. After fresh extraction PrimeTime re-times the design, and the loop repeats until nothing is left to fix.
  148. 148 Why is final timing signed off in PrimeTime rather than ICC2?Beginner: ICC2 is an optimizer: its timer runs inside placement, CTS and routing loops and is tuned for speed because optimization calls it over and over. PrimeTime is the dedicated analysis engine that the team agrees to trust, run on signoff parasitics with crosstalk, path-based recalculation and every scenario at once. Signing off in PT means one reference engine and one data set decide whether the chip meets timing.
  149. 149 What's the difference between graph-based and path-based analysis?Beginner: Graph-based analysis times every node once and keeps the worst arrival and the worst slew at each pin, even when they come from different inputs, so it is fast and pessimistic. Path-based analysis takes one path, drops the side inputs and recalculates the delays with the slews that belong to that path, so it is more accurate and slower. You find violations with GBA and use PBA to see how much of the remaining violation is real.
  150. 150 What is a timing derate, and where do you see it in a report?Beginner: A timing derate is a multiplier applied to calculated delays to cover on-chip variation: late delays are scaled up and early delays scaled down. In a PrimeTime report you only see it if you ask: `report_timing -derate` (PT) adds a Derate column next to each incremental delay. Reading that column tells you which factor was applied to which cell or net, and whether it is the one you meant.
  151. 151 Where does CRPR show up in a timing report, and why does it improve slack?Beginner: CRPR appears as a line called clock reconvergence pessimism on the capture side of a PrimeTime timing report, just after the clock network delay. It adds back the pessimism created when the shared part of the launch and capture clock paths was timed late for one and early for the other. Because it only removes pessimism, it can only improve slack.
  152. 152 How does crosstalk show up in a PrimeTime timing report?Beginner: With crosstalk analysis on, PrimeTime already includes crosstalk in every path delay, but you only see it separately if you ask. `report_timing -crosstalk_delta` (PT) adds a Delta column that shows the delay change on each victim net arc caused by switching neighbours. To find the nets that cause the most trouble across many paths, `report_si_bottleneck` (PT) ranks them.
  153. 153 How does clock uncertainty reduce setup and hold margin?Beginner: Clock uncertainty is a margin you add for clock effects you do not model, such as jitter or skew not yet known. For setup, PrimeTime subtracts it from the data required time, so data must arrive earlier; for hold, it adds it to the required time, so data must stay stable longer. Every picosecond of uncertainty is a picosecond of slack taken away.
  154. 154 Why must you run logic equivalence checking after every ECO?Beginner: Every ECO edits the netlist, and any edit can change function by mistake: a wrong library cell, a buffer on the wrong pin, a dropped inverter or a patch that does not match the new RTL. Timing and physical checks do not look at logic, so only equivalence checking proves the post-ECO netlist still computes what it should. It is quick for small ECOs and it is the only check that catches these bugs before silicon.
  155. 155 How do you read `report_qor`?Beginner: `report_qor` (PT) gives the one-page state of a design, organized by path group. Read it group by group, checking worst slack, TNS and number of violating paths, then the hold and design rule summaries; in PT, `report_constraint` (PT) lists the individual design rule violators behind those counts. The PT and ICC2 versions have the same idea and different numbers, because the engines, parasitics and settings differ.
  156. 156 What evidence proves timing is closed?Beginner: Timing is closed only when PrimeTime shows no violations in every signoff scenario and you can prove the analysis covered everything it should. That means clean constraints, no unexplained untested checks, no setup, hold or DRC violators, SI enabled, and any path saved by PBA confirmed with exhaustive analysis. A clean WNS number alone is not evidence.
  157. 157 What does PrimeTime's `write_changes` produce, and how is it applied in ICC2?Beginner: `write_changes` (PT) writes every netlist change made during the PrimeTime session as a change list, in a format chosen with `-format`. For ICC2 the format is icctcl, a Tcl script of netlist edits; ICC2 sources it, then places the changed cells with `place_eco_cells -eco_changed_cells` (ICC2) and reconnects them with `route_eco` (ICC2). The file is only a list of edits, so ICC2 still has to make them physically legal.
  158. 158 What does physical verification prove that timing signoff doesn't?Beginner: Timing signoff proves the circuit is fast enough. Physical verification proves the layout can be manufactured (DRC), that it is the circuit you meant to build (LVS), that nothing is electrically unsafe such as a floating gate (ERC), and that the power grid and wires survive real current (IR drop and EM). A block can meet timing in every corner and still be unbuildable or fail in the field, so tapeout needs both gates.
  159. 159 What's the difference between DRC, LVS and ERC?Beginner: DRC checks the layout geometry against the foundry manufacturing rules. LVS checks that the devices and connections extracted from the layout match the reference netlist. ERC checks for electrically unsafe connections, such as floating gates or untied wells, that can exist even when layout and netlist agree.
  160. 160 What is a DRC runset (deck), and who owns it?Beginner: A runset, often called a deck, is the program IC Validator executes: layer assignments, database checks and every design rule coded as PXL functions. The foundry writes and qualifies it for a specific process node and version, and the design team runs it without editing the rules. Checking against the wrong node, the wrong version or a locally modified copy is a real way to tape out a violating layout.
  161. 161 What does LVS actually compare?Beginner: LVS compares two netlists: the reference netlist the design was built from and a netlist IC Validator extracts from the layout geometry. It matches devices and their types and properties, how the device terminals connect into nets, and the ports at the top and at each equivalence point. It does not look at timing or rule spacing, only whether the layout is the same circuit.
  162. 162 What are the most common LVS failures?Beginner: The usual LVS failures are shorts, opens, missing or extra devices, and port or label mismatches. Shorts and opens come mostly from routing and ECO edits, device mismatches from wrong cell versions or wrong views at stream-out, and port problems from text labels. ICC2 can catch routing-level shorts and opens early; IC Validator gives the signoff answer.
  163. 163 How can a design pass LVS but fail ERC?Beginner: LVS only asks whether the layout matches the reference netlist. If the reference itself contains an electrical hazard, such as an unused gate input left unconnected, the layout faithfully reproduces it and LVS passes. ERC checks the extracted circuit for hazards like floating gates, so it fails on exactly the case LVS cannot see.
  164. 164 What is stream-out (GDSII/OASIS), and what must be in it?Beginner: Stream-out writes the finished layout as a GDSII or OASIS file, the format signoff tools and the foundry read. The file must contain the full layout: top-level routing and power, the real standard-cell and macro geometry merged in, metal fill, pin text, and every shape on the layer and datatype numbers the foundry expects. Anything missing or mis-mapped is invisible to signoff, so a clean check on an incomplete stream proves nothing.
  165. 165 Which IC Validator output files do you read first, and what's in each?Beginner: Read `cell.RESULTS` (ICV) first; the guide calls it the starting point for analyzing a run. Its header says `RESULTS: CLEAN` (ICV) or `RESULTS: NOT CLEAN` (ICV) for DRC, and `LVS Compare Results: PASS | FAIL` (ICV) plus a DRC-and-extraction line for LVS. Then go to `cell.LAYOUT_ERRORS` (ICV) for DRC detail, `cell.LVS_ERRORS` (ICV) for LVS detail and `cell.sum` (ICV) for run statistics.
  166. 166 What does a basic standalone IC Validator DRC and LVS run look like?Beginner: A standalone run is one shell command: `icv` (ICV), the layout file, its format, the top cell and the runset. For DRC that is `icv -i top.gds -f GDSII -c top drc_runset.rs` (ICV). For LVS you use the LVS runset and add the reference netlist with `-s top.sp -sf SPICE` (ICV). The runset, not a command option, decides whether the run is DRC or LVS.
  167. 167 What's the difference between IC Validator In-Design and a standalone IC Validator run?Beginner: IC Validator In-Design runs the IC Validator engine from inside ICC2 on the saved design library, through commands such as `signoff_check_drc` (ICC2), so you can find and fix violations without leaving implementation. A standalone run is the `icv` (ICV) command line on a GDS or OASIS file. In-Design is the fixing loop; standalone on the final stream is the signoff record.
  168. 168 How do you run signoff DRC from inside ICC2?Beginner: Point ICC2 at the IC Validator installation, set the foundry runset with `signoff.check_drc.runset` (ICC2), save the block because IC Validator reads the on-disk data, and run `signoff_check_drc` (ICC2). Results go to the run directory as `block.RESULTS` (ICC2) and `block.LAYOUT_ERRORS` (ICC2), and the error data file `signoff_check_drc.err` (ICC2) is stored in the design library for the error browser and automatic fixing.
  169. 169 Why are filler cells inserted, and what must be true first?Beginner: Filler cells fill the empty sites in standard-cell rows so that power rails, wells and implant layers run continuously and density rules on the base layers are met. The placement must be legal first: the guide says to confirm this with `check_legality` (ICC2) before insertion. After insertion, fillers must be connected to the power and ground nets with `connect_pg_net -automatic` (ICC2).
  170. 170 Decap fillers vs plain fillers: why not use decaps everywhere?Beginner: A decap filler is a capacitor between VDD and VSS that supplies local charge when nearby cells switch, which reduces dynamic voltage drop. A plain filler only keeps rails and wells continuous. Decaps are not free: each one leaks, and with modern thin gate oxides that leakage adds up, so at the finishing stage you place decaps where dynamic IR needs them and plain fillers elsewhere.
  171. 171 Why is metal fill required, and what do density rules check?Beginner: Chemical mechanical polishing flattens each metal layer, and it removes material unevenly when metal density varies across the die. Density rules check the fraction of each window covered by metal, with a minimum and a maximum, and often a limit on how much density can change between neighbouring windows. Metal fill adds floating shapes in empty areas so every window meets those limits.
  172. 172 Why insert fill only when timing is nearly clean?Beginner: Metal fill adds floating metal next to, above and below signal wires, and every piece adds capacitance. That changes the parasitics and so the delays, usually slowing paths. If you fill while timing is still moving, each timing fix disturbs the fill and each fill pass disturbs timing, so the ICC2 guide says the block should be close to meeting timing, with few or no DRC violations, before fill goes in.
  173. 173 What is an isolated via, and why is it a yield risk?Beginner: An isolated via is a via with no neighbouring via close enough to meet the technology's requirement. Lithography and etch are tuned for vias that sit in a pattern, so a lone cut prints with more size variation and is more likely to come out resistive or open, and one open via on a signal net is a dead net. In ICC2 you set the search range per via layer and run `signoff_fix_isolated_via -check_only true` (ICC2) before you let the tool change anything.
  174. 174 What is IR drop, and why does it hurt timing?Beginner: IR drop is the voltage lost across the resistance of the power grid when current flows through it, V = I x R added up along the path from the pad or bump to each cell's power pin. The ground side does the same in reverse, so VSS at the cell sits slightly above zero. The cell therefore runs on less than the nominal supply, its drive current falls, and paths that were timed at the library voltage come out slower than signoff assumed.
  175. 175 What's the difference between static and dynamic IR drop analysis?Beginner: Static IR drop uses each cell's average current over a cycle, so it shows the DC drop caused by grid resistance and is good at finding weak straps, missing vias and poor supply placement. Dynamic IR drop follows the current as it changes in time, when many cells switch together near a clock edge, so it catches short, deep dips shaped by decap, grid capacitance and the package. Run static first as a grid-quality check, then dynamic once placement, the clock tree and timing windows are real.
  176. 176 How do you judge whether IR drop is acceptable?Beginner: IR drop is acceptable when every loss the cell can see fits inside the voltage margin the library was characterised for. The rule is: grid drop (Vmax - Vmin on the supply net), plus ground rise, plus external supply variation, must be less than the gap between nominal VDD and the worst-case voltage used in the standard-cell library. If the slow corner is characterised at 0.72 V for a 0.80 V supply, everything together must fit in 80 mV.
  177. 177 What does EM signoff check: average, RMS or peak current?Beginner: EM signoff compares the current density in every wire segment, and the current per cut in every via, against the foundry's limits, and it can do that for three kinds of current: average, RMS and peak. Average current drives the slow drift of metal atoms that eventually opens a line, RMS tracks Joule heating, and peak guards against short high-current pulses. Static analysis only knows the average, dynamic analysis can check all three, and `perform emcheck` (RH) runs AVG, RMS, PEAK or all, with all as the default.
  178. 178 What are taps in rail analysis, and why must they touch metal?Beginner: Taps are ideal voltage sources placed on the PG network to stand in for the pads, bumps or block pins that feed it; every drop in the rail analysis is measured from them. They are virtual models, not part of the design, so a tap only does something if it touches a PG shape on its layer. A tap with no conductive path to the supply network has no effect on the analysis, and `create_taps` (ICC2) warns about it with RAIL-305.
  179. 179 How do you find missing vias and unconnected PG pins before IR analysis?Beginner: A missing via is a place where two PG shapes on different layers overlap but have no via in the overlap, and an unconnected pin shape is a PG pin that has no continuous physical path to an ideal voltage source. RedHawk Fusion finds both: set the options with `set_missing_via_check_options` (ICC2), save the block, then run `analyze_rail -voltage_drop static -check_missing_via -nets {VDD VSS}` (ICC2). The command reference says `-check_missing_via` requires `-voltage_drop`. Do it after the power structure is built and before `place_opt` (ICC2).
  180. 180 How do you read an IR-drop map?Beginner: Read an IR map as a picture of current flowing out from the supply points: the drop should grow smoothly from each tap toward the far and busy regions. The RedHawk manual lists what to look for: how many hotspots there are and whether they are where you expect, unexpected colour jumps that suggest missing straps or connections, unexpected black areas that mean missing data or connections, and whether the colour change from source to hotspot makes sense. In ICC2, load the map with `open_rail_result` (ICC2) after a RedHawk Fusion run.
  181. 181 Why must power calculation come before IR analysis?Beginner: IR drop is current times resistance, and the current comes from power calculation. If the libraries, activity or timing data behind the power numbers are wrong or missing, the currents are wrong, and a grid can look clean only because it is being fed too little current. So power is calculated and checked first, then the grid is extracted and analysed: `perform pwrcalc` (RH), `perform extraction` (RH), `perform analysis -static` (RH), or in ICC2 the rail library files and inputs are set before `analyze_rail` (ICC2).
  182. 182 What do ESD and latch-up checks protect against at signoff?Beginner: ESD checks confirm that every pad has a low-resistance discharge path through protection clamps, so a static discharge during handling, test or assembly flows through the clamps instead of through thin gate oxide. Latch-up checks confirm that well and substrate taps and guard rings are close enough that the parasitic PNPN structure inside CMOS cannot switch on and short VDD to VSS. Both protect against failures that timing, LVS and ordinary spacing checks do not see, and both are signed off with foundry rules and resistance-based checks.
  183. 183 What are DFM checks, and why are they "recommended" rather than mandatory?Beginner: DFM checks are foundry rules that go past the DRC minimums: larger via enclosures, redundant vias, longer line ends, wider spacing where there is room, and pattern matching for shapes known to lower yield. A layout that misses a recommended rule can still be built, so the foundry does not make these pass or fail; each fix buys yield at a cost in area, tracks or timing. You apply them where they are cheap and skip or waive them where they would hurt the design.
  184. 184 What goes into a tapeout handoff?Beginner: A tapeout handoff is the final layout plus the evidence that it is clean: a merged GDSII or OASIS stream with every cell, macro and fill shape, the final DRC, LVS and ERC results with an approved waiver list, IR and EM signoff reports, and whatever constraints or documents the foundry or chip owner requires. The stream must be the exact data that was verified, so it is written once from the final block and every signoff run points at that file. Any edit afterwards means rerunning the checks.
  185. 185 Why is physical signoff so strict? What does a missed defect cost?Beginner: Once masks are made, the layout cannot be patched: a defect that escapes means new masks, a new wafer run and months before corrected silicon is back. Advanced-node mask sets are very expensive, and the schedule loss often costs more than the masks because the product misses its market window. So physical signoff treats every unexplained DRC, LVS, ERC, IR or EM result as a blocker until it is fixed or formally waived.
  186. 186 Why does thermal analysis matter for signoff?Beginner: Temperature changes the numbers every other signoff check depends on. Hotter metal has higher resistance, so IR drop grows; EM limits are tied to temperature and allowed current falls as metal heats; and leakage rises with temperature, adding power and more heat. Thermal analysis, run in ICC2 with Kelvin through `analyze_thermal` (ICC2), shows where the die is hotter than the temperature the other analyses assumed.
  187. 187 What must be clean before a block is handed off for tapeout?Beginner: A block leaves physical verification only when every check has run on the final data and is clean or formally waived: DRC clean or waived, LVS PASS, ERC clean, antenna clean, density met, isolated vias fixed, IR drop and EM inside budget, and fill and extraction redone after the last change with timing rechecked. The order matters, because fill and ECOs change the layout; the checks must come after the last edit, not before it.

Preparing for a physical design interview? Take the answers with you.

  • All 1109 questions and answers as 4 PDF books: PnR, STA, MMMC and Low Power.
  • A clickable table of contents, so you can search and jump offline.
  • Delivered by email within seconds of payment. Full refund if the files fail to arrive or open.
See what is inside the bundle · ₹349Physical Design & Planning HandbookComplete library