What design rule constraints does CTS actually have to meet, separate from timing?

Short Answer

CTS has its own DRC set, independent of setup/hold: max transition, a skew requirement, max capacitance, and max fanout. These aren't optional nice-to-haves -- a clock tree that meets setup and hold perfectly but violates max transition on a clock net is still a broken tree, because electrical DRC violations are checked and reported separately from timing violations.

Technical Explanation

• CTS design rule constraints are: max transition, a skew requirement, max capacitance, and max fanout -- a distinct check set from setup/hold timing.
• A clock tree can pass every setup/hold check and still fail CTS DRC if a clock net violates max transition or max capacitance -- these are checked and reported independently.
• This is exactly why report_constraint [PrimeTime: not report_timing] is the command that surfaces these violations -- timing-clean and DRC-clean are two separate claims about the same tree.

Follow-up Question & Model Response

"Why would max fanout specifically matter more on a clock net than on an ordinary data net?"

Candidate Model Response: Clock nets typically drive far more sequential loads than a data net drives combinational loads, so a fanout violation on a clock net risks slew/transition problems across a much larger fraction of the design at once -- the blast radius of one bad clock net is structurally larger.