What is a floorplan, and what problem does it solve?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
A floorplan is the first step where a logically valid netlist gets turned into a physical plan — where boundaries, rows, macros, pins, and reserved channels actually live in physical space, obeying real technology and library rules. The best analogy is arranging rooms and hallways in a building before you furnish anything — except unlike a building sketch, every object here has to satisfy hard, mechanically-checkable rules (site grids, layer directions, spacing rules), not just aesthetic judgment.
Technical Explanation
- The core problem it solves: proving, as early as possible, that the design can plausibly fit together and connect — before you sink hours into detailed placement and routing on a floorplan that was never going to work.
- What a floorplan explicitly does NOT do: it doesn't perform detailed cell-level optimization, it doesn't build the clock tree, it doesn't route anything, and it doesn't do signoff extraction or timing closure. Those are all later stages that depend on the floorplan being right first.
- Getting the floorplan wrong is expensive precisely because everything downstream inherits its assumptions — a bad macro placement or wrong aspect ratio discovered during detail routing means re-doing a huge amount of downstream work, whereas catching it at the floorplan stage costs almost nothing by comparison.
Visual Verification
Floorplanning establishes the physical framework of the chip, defining core boundaries, standard-cell placement rows, hard-macro placement, I/O pin coordinates, and power grid corridors.
Formula Or Decision Rule
Decision rule: a floorplan is ready only when legality and early quality evidence agree.
What To Check
- Warning sign: A boundary exists but rows, macros, pins, or routing corridors have no credible plan.
- Inspect: choose one affected region, macro, row, pin, path, or net and trace the physical cause.
- Correct: Create and review the missing physical intent, then rerun the same checks.
Command Checks & Actions
report_design-floorplan: reports the floorplan state understood by the tool
Run only the commands needed for this question. Save the report with the floorplan version and analysis context.
Healthy, Suspicious & Hard-stop Results
- Healthy: A floorplan turns a logically valid design into a physical plan for boundaries, rows, macros, pins, channels, and reserved resources. It is the first proof that the design can plausibly fit and connect.
- Hard stop: required legality or physical feasibility is missing or unexplained.
Common Mistake
The Trap: Do not hide the symptom with an arbitrary utilisation, halo, channel, blockage, pin move, or die-size change.
What The Interviewer Is Testing
” to measurable physical evidence and an owned correction.
Physical Design & Planning Handbook
Master ASIC Physical Design Planning & Floorplanning
Dive into 14 comprehensive chapters covering netlist sanity, FinFET grids, macro placement, power grids, CTS, and timing budgeting.
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