How can a floorplan affect timing before placement is complete?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
Even before a single standard cell is placed, the floorplan is already shaping how long wires will eventually have to be — and wire length translates almost directly into estimated interconnect delay. Physical distance matters most obviously: two logically connected blocks placed far apart on the die will need longer wires than the same two blocks placed close together, even though the logic connecting them hasn't changed at all.
Technical Explanation
- Macro pin side matters too — if a macro's relevant pin faces away from where the connecting logic actually sits, the effective route has to detour around the macro body, adding length the straight-line distance wouldn't suggest.
- Hierarchy crossings and feedthroughs both add real delay and real routing complexity that a naive "distance on the floorplan" estimate can miss if you're not accounting for them explicitly.
- Congestion matters at this early stage too — a route through a congested region may end up longer or more buffered than the same logical connection would need in an uncongested region.
- Buffering opportunity is part of the picture as well — floorplans that leave clean, unobstructed channels give the tool room to insert repeaters efficiently; floorplans that don't, force worse buffering solutions later.
- One important caveat: at this stage, clock-source location and clock-tree assumptions are still just estimates — CTS hasn't run yet, so any "clock timing" conclusion drawn from the floorplan alone is provisional, not final. And for a fair comparison between floorplan alternatives, always use identical constraints, scenarios, libraries, and estimation settings — otherwise you're not really comparing the floorplans, you're comparing your settings.
Visual Verification
Physical floorplanning determines wirelengths between communicating blocks; excessive physical separation adds wire resistance and capacitance (RC delay) that timing optimization cannot overcome.
Formula Or Decision Rule
Decision rule: compare alternatives with the same estimation method; never call early estimated timing “closure”.
What To Check
- Warning sign: Timing improves only because a different scenario or estimation setup was used.
- Inspect: choose one affected region, macro, row, pin, path, or net and trace the physical cause.
- Correct: Restore identical analysis context, compare representative paths, and document the physical cause of any change.
Command Checks & Actions
- estimate_timing: performs early virtual timing estimation
report_timing-path_type full_clock_expanded: reports timing paths in the active analysis context
Run only the commands needed for this question. Save the report with the floorplan version and analysis context.
Healthy, Suspicious & Hard-stop Results
- Healthy: Distance, macro pin side, detours, hierarchy crossings, feedthroughs, congestion, buffering opportunity, and clock-source location change estimated interconnect delay.
- Hard stop: required legality or physical feasibility is missing or unexplained.
Common Mistake
The Trap: Do not hide the symptom with an arbitrary utilisation, halo, channel, blockage, pin move, or die-size change.
What The Interviewer Is Testing
” to measurable physical evidence and an owned correction.
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