How does Scan Chain Re-ordering work, and why is ScanDEF necessary during placement?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
Synthesis stitches scan flip-flops together purely by RTL naming order (reg_a[0] → reg_a[1] → ... → reg_b[0]) with zero awareness of where those flops will eventually sit on the die. Once placement happens geographically, that naming-order chain can become a routing nightmare — reg_a[0] might land top-left while reg_a[1] lands bottom-right, forcing the scan chain to criss-cross the entire die.
Technical Explanation
- Synthesis stitches scan flip-flops together purely by RTL naming order (reg_a[0] → reg_a[1] → ... → reg_b[0]) with zero awareness of where those flops will eventually sit on the die.
- Once placement happens geographically, that naming-order chain can become a routing nightmare — reg_a[0] might land top-left while reg_a[1] lands bottom-right, forcing the scan chain to criss-cross the entire die.
- ScanDEF is what rescues this: it's a separate file describing the logical scan architecture (chain names, SI/SO top-level ports, and which registers are safely re-orderable) so the placement tool knows it's allowed to re-stitch connections without breaking test intent.
- After placement legalization, the tool re-solves the stitching almost like a mini traveling-salesman problem — reconnecting SO→SI between geographically nearest-neighbor flops instead of RTL-order neighbors — typically cutting scan routing wirelength by 60–80%.
- This re-stitching isn't a free-for-all: it must respect clock domain and edge boundaries — the tool will never stitch a negative-edge flop directly before a positive-edge flop without inserting a lockup latch, because that would break scan-shift timing.
- Net effect: ScanDEF turns a naming-order chain (efficient for RTL/DFT tools) into a placement-order chain (efficient for silicon), while still producing something ATPG can trust.
Common Mistake
The Trap: Allowing the placer to re-order scan flops across different power domains or clock domains without lockup latches, resulting in clock race hold failures and ATPG test pattern corruption.
Follow-up Question & Model Response
"What happens to manufacturing test patterns after scan chain re-ordering?"
Candidate Model Response: The physical design tool writes out an updated ScanDEF file. The DFT team feeds this updated ScanDEF back into ATPG tools (like TetraMAX / Tessent) to regenerate matching scan test patterns.
Practical Example
Loading ScanDEF & Re-ordering Scan Chains:
# Synopsys ICC2: Read synthesis ScanDEF and enable scan re-ordering
read_def design_scan.def
set_app_options -name place_opt.scan.reorder -value true
# Re-order scan chains based on legalized coordinates
reorder_scan_chains
write_def -version 5.8 -scan output_scandef.defPnR Flow Mentor Guide
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