How does Physical Register Retiming work during placement, and how is Formal Verification maintained?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
When a combinational logic cone between two pipeline stages has badly imbalanced delay, sizing and buffering alone often can't close setup timing — retiming actually moves the register boundary itself to rebalance the pipeline. Mechanically: forward retiming slides a flip-flop from a logic gate's input pins to its output pin, and backward retiming does the reverse — moving a register from a gate's output back across to all of its input pins — reshaping where pipeline stage boundaries physically sit.
Technical Explanation
- When a combinational logic cone between two pipeline stages has badly imbalanced delay, sizing and buffering alone often can't close setup timing — retiming actually moves the register boundary itself to rebalance the pipeline.
- Mechanically: forward retiming slides a flip-flop from a logic gate's input pins to its output pin, and backward retiming does the reverse — moving a register from a gate's output back across to all of its input pins — reshaping where pipeline stage boundaries physically sit.
- Retiming also has to preserve correct power-up behavior: the engine computes new, equivalent reset/preset initialization vectors so the retimed circuit still powers up into an identical functional state, even though the registers moved.
- The formal-verification challenge is real: because register names, counts, and even boundaries change across the transformation, ordinary combinational-equivalence formal checking simply doesn't apply anymore — you need sequential equivalence checking instead.
- The tool solves this by writing an automated Setup Verification File (SVF) documenting every register-shift operation, which sequential formal tools (Formality, Conformal) consume to prove the retimed netlist is still functionally equivalent to the original.
Common Mistake
The Trap: Retiming registers with asynchronous resets without exporting the SVF file. Formality / Conformal will fail with hundreds of non-equivalent register state mismatches.
Follow-up Question & Model Response
"Why can't registers with multiple fanouts to different clock domains be retimed easily?"
Candidate Model Response: Retiming across multiple clock domains or async interfaces alters CDC synchronizer depth and breaks metastability guarantees.
Practical Example
Enabling Adaptive Retiming in place_opt:
# Synopsys ICC2: Record SVF verification file and enable adaptive retiming
set_svf design_retiming.svf
set_app_options -name opt.adaptive_retiming.enable -value true
place_opt
set_svf -offPnR Flow Mentor Guide
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