ExpertQuestion 17 of 161

A bulk input-delay command constrained the clock port. What is the impact?

From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide

Short Answer

A bulk set_input_delay [all_inputs]-style command is a footgun on any design where the clock is also a top-level port, because it accidentally treats the clock pin as ordinary data. The clock port is supposed to be excluded from data-path constraints โ€” it defines the timing reference itself, it isn't a signal that arrives relative to that reference.

Technical Reference DiagramA bulk input-delay command constrained the clock port. What is the impact?

Technical Explanation

  • Once input delay is applied to the clock port, the tool can start modeling misleading boundary timing paths through the clock pin as if it were a data input, producing bogus arrival/required-time relationships that don't correspond to anything real in the design.
  • g. filtering all_inputs against all_clocks before applying set_input_delay.
  • The failure mode is sneaky because it doesn't crash or obviously error โ€” it just quietly pollutes the timing report with phantom paths, and an engineer chasing a "why is there a path through my clock pin" mystery can burn real time before realizing the root cause is a constraint-scope mistake.
  • General lesson: any bulk/wildcard constraint command needs a sanity check against object class (is this actually a clock? a power pin? ) before it's trusted โ€” bulk convenience commands are exactly where selector-scope bugs like this hide.

What To Check

  • Warning sign: report_ports shows input delay on clocks, resets, or non-data controls.
  • Inspect: Keep at least two possible causes open, then use one named object and the active mode or scenario to separate them.
  • Correct: Replace the wildcard with explicit data-port collections, reload the SDC cleanly, and verify membership.

Command Checks & Actions

  • report_ports -input_delay [get_ports *]: shows boundary constraints and electrical assumptions
  • report_clocks: shows clock definitions and relationships

Run the commands in order. Each line answers a separate part of the check.

Healthy, Suspicious & Hard-stop Results

  • Expected: It models the clock port as ordinary data and can create misleading boundary paths or constraints; selector scope is defective.
  • Stop before floorplanning when required logic or timing coverage is missing or unexplained.

Common Mistake

The Trap: Do not assume the check passed just because ICC2 continued. Fix or narrowly justify the named objects, then rerun the same command.

What The Interviewer Is Testing

Be ready to explain why this matters before floorplanning.

Follow-up Question & Model Response

Model response: โ€œI would save the report, inspect one affected object in the correct block and scenario, and make or request this correction. โ€

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