ExpertQuestion 18 of 161

A negative output minimum delay appears. Is it automatically wrong?

From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide

Short Answer

No — a negative minimum output delay is not automatically a bug; the sign can legitimately follow the receiving interface's own hold convention, so seeing a minus sign shouldn't trigger an automatic "fix" reflex. What actually matters is whether the value was deliberately derived from the interface spec and correctly associated with the right clock and clock edge — a negative number that's correctly derived is fine; a negative number that just fell out of a copy-pasted constraint template is not.

Technical Reference DiagramA negative output minimum delay appears. Is it automatically wrong?

Technical Explanation

  • Treat every unusual-looking timing constraint (not just negative min delays) this way: verify it against the documented interface protocol before assuming it's either right or wrong based on its sign alone.
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  • Getting this wrong in either direction is costly: reflexively "fixing" a legitimate negative value breaks the actual interface timing, while ignoring an illegitimate one lets a real hold problem slip through disguised as an intentional constraint.

What To Check

  • Warning sign: An engineer changes the sign only to make hold reports look familiar.
  • Inspect: Keep at least two possible causes open, then use one named object and the active mode or scenario to separate them.
  • Correct: Return to the interface equation and STA owner, preserve justified sign intent, and inspect the boundary min path.

Command Checks & Actions

  • report_ports -output_delay [get_ports *]: shows boundary constraints and electrical assumptions
  • report_timing -delay_type min -to <output_port>: shows a path and its timing calculation

Run the commands in order. Each line answers a separate part of the check.

Healthy, Suspicious & Hard-stop Results

  • Expected: No; the sign can follow the receiving interface hold convention, but it must be derived and associated with the correct clock and edge.
  • Stop before floorplanning when required logic or timing coverage is missing or unexplained.

Common Mistake

The Trap: Do not assume the check passed just because ICC2 continued. Fix or narrowly justify the named objects, then rerun the same command.

What The Interviewer Is Testing

Be ready to explain why this matters before floorplanning.

Follow-up Question & Model Response

Model response: “I would save the report, inspect one affected object in the correct block and scenario, and make or request this correction. ”

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