How do you verify output loads?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
An output load value represents what your block has to drive once its signal leaves the boundary โ the receiver's input capacitance plus whatever the package/board adds on top. A realistic number comes from the actual receiver device and package assumptions, not a rule-of-thumb default carried over from a different interface.
Technical Explanation
- Units are an easy silent error โ mixing up pF and fF by a factor of 1000 will pass syntax checking and quietly distort every downstream optimization decision on that output.
- Correlate the load value against the correct mode and check whether it needs separate min/max analysis โ an output that's lightly loaded in one operating mode and heavily loaded in another needs both cases modeled, not one averaged value.
What To Check
- Warning sign: Loads are missing, scaled incorrectly, or copied uniformly across unlike interfaces.
- Inspect: Compare one named object across the related reports; the same object should tell a consistent story.
- Correct: Correct the producing interface model and inspect design-rule and timing behaviour at representative outputs.
Command Checks & Actions
- report_ports -design_rule [get_ports *]: shows boundary constraints and electrical assumptions
- report_user_units: shows the units ICC2 uses when reading and printing values
Run the commands in order. Each line answers a separate part of the check.
Healthy, Suspicious & Hard-stop Results
- Expected: Correlate load values with receiver and package assumptions, units, modes, and min/max analysis needs.
- Stop before floorplanning when required logic or timing coverage is missing or unexplained.
Common Mistake
The Trap: Do not assume the check passed just because ICC2 continued. Fix or narrowly justify the named objects, then rerun the same command.
What The Interviewer Is Testing
Be ready to explain why this matters before floorplanning.
Follow-up Question & Model Response
Model response: โI would save the report, inspect one affected object in the correct block and scenario, and make or request this correction. โ
Physical Design & Planning Handbook
Master ASIC Physical Design Planning & Floorplanning
Dive into 14 comprehensive chapters covering netlist sanity, FinFET grids, macro placement, power grids, CTS, and timing budgeting.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.

Continue practising