What are a placement site, a standard-cell row, and cell height?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
A placement site is the smallest reusable unit of legal placement geometry — a row is just that unit tiled repeatedly across the floorplan, and a standard cell has to occupy a whole number of compatible sites, in a legal orientation. For a simple single-height library, every cell shares the same row-compatible height but varies in width (e.g., roughly 0.192 µm site-width increments) — that width quantization is exactly what lets the placer snap cells onto a clean, regular legal grid.
Technical Explanation
- A placement site is the smallest reusable unit of legal placement geometry — a row is just that unit tiled repeatedly across the floorplan, and a standard cell has to occupy a whole number of compatible sites, in a legal orientation.
- For a simple single-height library, every cell shares the same row-compatible height but varies in width (e.g., roughly 0.192 µm site-width increments) — that width quantization is exactly what lets the placer snap cells onto a clean, regular legal grid.
- Don't confuse the physical cell boundary with transistor width — the cell boundary is a library design choice that has to fit technology rules, and it bundles in devices, internal routing, pins, and power access, not just raw silicon.
- Multi-height and mixed-height libraries add real compatibility/legalization rules on top of this, and while alternating row orientation can support power-rail alignment, any mirroring you apply has to be something the cell/site symmetry and power architecture actually allow — always verify a cell's site association, height, permitted orientations, and any special placement constraints before assuming it's interchangeable.
Command Checks & Actions
read_def block.defImports the site array from the DEF's ROW section, which is what actually defines row height and site width for the design.
create_tap_cells -lib_cell mylib/tap -distance 30Inserts tap cells row by row. Its own default behavior -- starting at row edges, snapping to row height -- only makes sense once site, row, and cell height are understood.
Common Mistake
The Trap: Candidates often mistakenly confusing placement-site width with metal routing pitch merely because their numeric values happen to match in one example.
Follow-up Question & Model Response
"Why can a cell fail legalization even when it fits inside the core?"
Candidate Model Response: It can violate site alignment, row height, orientation, overlap, region, or power-domain requirements.
Practical Example
Tapeout Scenario: A 0.192 um-wide cell fits four 0.048 um site steps. A placement origin at 0.096 um is two steps from a zero-offset row origin; an origin at 0.100 um is not. This is a teaching grid, not a universal library dimension.
PnR Flow Mentor Guide
Master the Physical Design Implementation Flow
Read the complete 8-chapter PnR Flow Mentor Guide free on the web — library setup through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO, all the way to stream-out.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.
Continue practising