How do manufacturing, placement, routing, and FinFET grids differ?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
These four grids each constrain a different thing, and satisfying one doesn't automatically satisfy the others: the manufacturing grid quantizes what coordinates are even representable, placement sites constrain legal cell origins, routing tracks suggest wire centerlines, and the FinFET grid constrains cell/boundary alignment to the fin pitch. The manufacturing grid is usually the finest of the four — being on it only means a coordinate is a legal, representable geometric step, not that it's a legal cell origin, and being on a legal placement site doesn't prove a pin is routable or that a macro boundary satisfies every device-alignment rule.
Technical Explanation
- These four grids each constrain a different thing, and satisfying one doesn't automatically satisfy the others: the manufacturing grid quantizes what coordinates are even representable, placement sites constrain legal cell origins, routing tracks suggest wire centerlines, and the FinFET grid constrains cell/boundary alignment to the fin pitch.
- The manufacturing grid is usually the finest of the four — being on it only means a coordinate is a legal, representable geometric step, not that it's a legal cell origin, and being on a legal placement site doesn't prove a pin is routable or that a macro boundary satisfies every device-alignment rule.
- Treat each grid as its own rule with its own origin/offset, spacing, applicable object types, and orientation convention — check the technology and library definitions together, and if multiple grids constrain the same object, it has to satisfy all of them simultaneously. It's unsafe to collapse all four into "one pitch I remember."
- When an import produces off-grid geometry, first identify which grid was actually violated before snapping anything — rounding blindly can quietly change spacing, enclosure, macro alignment, or port access. Use the tool's proper legalization/grid-checking flow and inspect the affected geometry afterward rather than trusting the snap silently worked.
Command Checks & Actions
set_technology -node 7Applies the node's manufacturing, placement, routing, and FinFET grid definitions together as one coordinated setting.
analyze_lib_cell_placement -lib_cells <lib_cells>Tests whether library cells are actually legally placeable against these grids, at real or randomly sampled sites, turning "the grids differ" from a definition into a testable pass/fail result.
Common Mistake
The Trap: Saying a point is simply “on-grid” without naming the grid and the object rule being checked.
Follow-up Question & Model Response
"Can a routing pin be off a track center and still be accessible?"
Candidate Model Response: Yes, if legal overlap and via/access geometry permit a connection; pin access is more than center-coordinate equality.
Practical Example
Tapeout Scenario: A coordinate of 0.100 um lies on a zero-offset 0.001 um manufacturing grid. It is not on a zero-offset 0.048 um site grid, because 0.100/0.048 is not an integer. The finer-grid pass does not imply a placement-grid pass.
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