What are Spare Cells, and why must they be distributed uniformly pre-CTS?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
Spare cells are unconnected, uncommitted logic gates dropped into the die before CTS, purely as insurance — if a functional bug turns up after tapeout, you may be able to fix it without a full new mask set. A brand-new mask set costs millions and takes months; if spare gates already exist on silicon nearby, the fix can sometimes be done with just a metal-and-via change, which is roughly 5–10x cheaper and 3x faster.
Technical Explanation
- Spare cells are unconnected, uncommitted logic gates dropped into the die before CTS, purely as insurance — if a functional bug turns up after tapeout, you may be able to fix it without a full new mask set.
- A brand-new mask set costs millions and takes months; if spare gates already exist on silicon nearby, the fix can sometimes be done with just a metal-and-via change, which is roughly 5–10x cheaper and 3x faster.
- Every spare cell's inputs must be tied off to TIEHI/TIELO — a floating CMOS gate input isn't just useless, it can draw excess subthreshold leakage or even oscillate.
- Uniform distribution isn't optional: a bug can surface anywhere on the die, and a spare gate stranded far from the fix site means routing a wire across a long distance — which adds RC delay and crosstalk risk right when you need a clean, low-risk fix. That's also why they're placed pre-CTS and marked
dont_touch, so later optimization can't quietly delete or relocate them.
Common Mistake
The Trap: Leaving spare cell inputs floating. Floating gate inputs float to intermediate threshold voltages, turning on both PMOS and NMOS transistors simultaneously and causing massive static leakage dissipation.
Follow-up Question & Model Response
"What standard cell gate types make up an ideal spare cell module?"
Candidate Model Response: A balanced spare cell module includes universal logic gates (NAND2, NOR2, INV), multiplexers (MUX2), and D-flip-flops (DFF) to implement both combinational corrections and state additions.
Practical Example
Spare Cell Insertion & Tie-Off:
# Synopsys ICC2: Add spare cell modules uniformly across standard cell rows
add_spare_cells -cell_name SPARE_BLOCK -num_cells 200 -uniform
# Ensure all spare inputs are tied to TIEHI/TIELO and locked
connect_tie_cells -objects [get_pins spare_*/A*] -tie_low_lib_cell TIELO
set_dont_touch [get_cells spare_*]PnR Flow Mentor Guide
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