Derive why MIS is scoped to hold and not setup, using the two NAND switching directions.

Short Answer

Multi-input switching (MIS) is a delay adjustment applied when two or more inputs of a gate switch close together in time. On a 2-input NAND, both inputs falling together speeds up the rising output, which shortens the data path's minimum delay - the exact quantity a hold check uses - so MIS is scoped to hold, not setup.

Technical Explanation

• What MIS models. Multi-input switching (MIS) is a delay correction for the case where two or more inputs of a multi-input gate transition within a narrow time window of each other, instead of one at a time. A gate's characterized delay normally assumes a single switching input; MIS adjusts for the accelerated or slowed behavior when several switch together.
• The NAND mechanism, both inputs falling. A 2-input NAND has two NMOS transistors in series pulling its output low, and two PMOS transistors in parallel pulling it high. When both inputs fall together, both parallel PMOS transistors turn on at once, charging the output faster than a single-input transition would - where only one PMOS conducts alone while the other input stays high - so the rising edge accelerates.
• Why that lands on hold, not setup. A hold check uses the path's minimum delay - how fast data can possibly arrive. An accelerated rising edge shortens that minimum delay directly, tightening hold margin and creating a hold race the tool must catch. Without MIS analysis, the library only has the slower single-input-switching delay to work with, so the hold check is optimistic - it assumes data arrives later than it actually can.
• The other direction. Both inputs rising together turns on the two series NMOS pull-down transistors at once, which can slow the falling output relative to a single-input transition, because the series stack's shared internal node has less time to pre-discharge before both transistors conduct. That direction affects the path's maximum delay - the setup-relevant quantity - but setup paths are typically long enough, many gate stages deep, that one gate's slowdown is a small fraction of the total and rarely decisive.
• The result. MIS characterization data in modern PrimeTime flows is scoped specifically to hold-critical analysis, because the switching-direction physics of a NAND (and similarly structured gates) makes the hold-relevant acceleration the dominant, design-affecting case.
• When it actually applies. The tool only applies MIS derating when it determines the arrival windows of the multiple inputs genuinely overlap - two inputs switching far apart in time do not trigger it.

Follow-up Question & Model Response

How does PrimeTime decide whether two inputs "switch close enough together" to trigger MIS, rather than treating every multi-input gate as always MIS-derated?

Candidate Model Response: PrimeTime evaluates the arrival-time switching windows of the multiple inputs on that arc - the range between their earliest and latest possible transition times under the analysis mode in effect. MIS derating is only applied when those windows genuinely overlap, meaning both inputs could plausibly be switching during the same interval. If one input's window is well separated in time from the other's, the tool has no basis for assuming simultaneous switching and reports the ordinary single-input delay instead. This keeps MIS from over-applying pessimism to gates whose inputs are timed apart by design.