Level 3: PrimeTime Analysis & Debugging

Advanced STA Interview Questions

Analyze PrimeTime-specific precedence, annotation, variation, constraints, and clock-network behavior in realistic signoff scenarios.

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Analyze PrimeTime-specific precedence, annotation, variation, constraints, and clock-network behavior in realistic signoff scenarios.

  1. 01 Explain the precedence interaction when an explicit -sms_scenarios option and an active push_sms_scenario context both apply to a command.Advanced: A DVFS scenario (one voltage/frequency operating point in a design that switches between several) can reach a command two ways: typed on the command as `-sms_scenarios` (PT), or inherited from a `push_sms_scenario` (PT) context around it. The explicit option always wins, and the pushed context is ignored for that command, not merged with it.
  2. 02 Why is report_ocvm -type pocvm -cell_delay -list_not_annotated an important pre-signoff check, and what does a missing cell imply?Advanced: The command lists cells with no POCV (parametric on-chip variation, a statistical way of modeling how much a cell's delay can vary) coefficient or distance data - cells that quietly fall back to zero variation. Any path through one of them has under-modeled spread, so its reported corner is optimistic and can hide a real violation.
  3. 03 A design has both set_annotated_delay on some arcs and a full SPEF read. How does PrimeTime resolve the overlap, and what's the debugging implication?Advanced: Annotated delays win by precedence, not by which one was applied last. `set_annotated_delay` (PT) sits at tier 1 and SPEF-derived parasitics sit at tier 3, so on any arc where both apply, PrimeTime uses the annotated value and ignores the SPEF-derived delay for that arc.
  4. 04 Why is a per-cell IR-drop annotation treated as uncorrelated with the main rail, and what's the consequence?Advanced: Correlation is a physical claim, not a convenience setting. A per-cell IR-drop annotation (a local voltage droop measured at one instance's supply pin) describes an independent local event, so PrimeTime compares the full worst-case voltage difference across it instead of assuming the driver and load move together.
  5. 05 Derive why MIS is scoped to hold and not setup, using the two NAND switching directions.Advanced: Multi-input switching (MIS) is a delay adjustment applied when two or more inputs of a gate switch close together in time. On a 2-input NAND, both inputs falling together speeds up the rising output, which shortens the data path's minimum delay - the exact quantity a hold check uses - so MIS is scoped to hold, not setup.
  6. 06 How does PrimeTime model and analyze clock networks, including latency and uncertainty?Advanced: PrimeTime propagates a defined clock waveform through the network to find each register's latency - source latency plus network latency - and derives skew from the differences. On top of that it adds clock uncertainty for jitter and margin, using ideal latency pre-CTS (clock tree synthesis) and real propagated latency post-CTS.
  7. 07 Explain the interaction between CCS receiver modeling and max-transition/max-capacitance DRC characterization.Advanced: CCS (composite current source, a more detailed cell-timing model than the older NLDM tables) adds its own receiver-capacitance and driver tables. The safe max_capacitance limit is the lowest maximum load index across all of them, and the safe max_transition limit is the lowest maximum slew index across NLDM, CCS driver and CCS receiver_capacitance2 - set it from NLDM alone and DRC can pass while delay calculation quietly extrapolates.
  8. 08 Explain the trip from a StarRC multicorner GPD to a single-corner PrimeTime annotation, and why multicorner extraction is worth it.Advanced: StarRC run with SIMULTANEOUS_MULTI_CORNER: YES extracts several RC corners in one pass into a single multicorner GPD (Galaxy Parasitic Database) file. PrimeTime then selects one corner with `set_app_var parasitic_corner_name cworst_CCworst` (PT) and reads it - the payoff is that the expensive geometric extraction work happens once and is reused across every corner.
  9. 09 Explain the interaction between POCV and clock reconvergence pessimism removal on a clock path - do they double-count?Advanced: No - they correct different artifacts. CRPR (clock reconvergence pessimism removal) removes the double-counted delay on the clock segment shared by launch and capture; POCV's graph-merging pessimism removal separately removes the stochastic-max inflation that occurs where several fan-in distributions converge. A clock path needs both active.
  10. 10 Why must all libraries in the scaling groups have CCS noise data specifically, beyond CCS timing?Advanced: Because SMVA (statistical multi-voltage analysis) is a full signoff feature covering noise across voltage combinations, and voltage-dependent noise response - crosstalk bumps and immunity - is captured only in a library's CCS noise models, not its CCS timing tables. A scaling group missing noise data on even one member library breaks the interpolation.
  11. 11 A path in a switchable domain reports the wrong voltage after a power switch. How do you debug it?Advanced: Trace voltage in the same order PrimeTime resolves it: `report_power_switch` (PT) for the switch's On State condition, `report_power_network` (PT) for the topology it feeds, `report_supply_net` (PT) for the output net's voltage, then `report_timing -voltage` (PT) or the pg_pin_info attribute on the cells. The most common root cause is a missing set_voltage on the switch's output net.
  12. 12 A team proposes leaving clocks ideal (skipping propagated timing) post-CTS to save runtime near a deadline. How do you respond?Advanced: Refuse it. An ideal clock uses estimated or zero network latency, not the real skew of the clock tree that clock tree synthesis (CTS) just built, so it silently mis-times every path in the domain - hold checks worst of all, since hold is dominated by skew. Solve runtime with parallelism and prioritization instead, not by falsifying the clock model.
  13. 13 How do generated clocks interact with source latency, and how does edge-specific source latency propagation work?Advanced: A generated clock's source latency is inherited from its master, not specified independently - it is the master clock's insertion delay from its origin down to the generated clock's source pin. PrimeTime computes it automatically when the master is propagated, and tracks it separately per edge because a clock network's rise and fall delays are not always equal.
  14. 14 Compare disabling a path with case analysis, set_disable_timing and set_false_path - mechanism, blast radius, and when each is the right tool.Advanced: Case analysis sets a fixed value and structurally kills every arc that value controls; set_disable_timing removes one specific arc or object entirely; set_false_path removes exactly the point-to-point paths named. There is an efficiency ladder favoring them in that order.
  15. 15 Explain why "only internal nets are annotated in SDF" and how that shapes your verification.Advanced: The SDF (standard delay format) standard defines INTERCONNECT delays only for nets internal to the design. A net connected directly to a primary input or output port describes the environment outside the design, and that is modeled instead with set_input_delay and set_output_delay - so non-annotation there is correct behavior, not a coverage gap.
  16. 16 Why does setting only -setup 2 create a hold problem? Walk the edges.Advanced: Because a hold check's reference edge is derived from the same-cycle setup relationship, not defined independently. Moving the setup capture edge out by one cycle drags the implied hold edge forward with it, demanding data stay stable for a full extra cycle the real hardware never needs.
  17. 17 Walk through how PrimeTime performs a full timing update internally, from reading data to computing slack.Advanced: It builds a timing graph after link_design, propagates the defined clocks to every register's clock pin, calculates each arc's delay with slew propagated stage to stage, propagates arrival times forward and required times backward while honoring exceptions, then subtracts the two to get slack at every point.
  18. 18 Construct a scenario where forgetting sequential propagation makes a scan-disable silently ineffective.Advanced: Set `set_case_analysis 0 [get_ports SCAN_MODE]` (SDC) without enabling sequential case-analysis propagation on the scan flops, and the constant stops at their TE pins. It never crosses the flop, so the CP-to-TI scan arcs stay enabled and the scan chain keeps being timed - with no warning that anything is wrong.
  19. 19 Why might report_mode show a mode ENABLED with Reason default even though you set case analysis intending to disable it?Advanced: Reason default describes the selection mechanism, not the mode - it means nothing actively chose or excluded that mode, so it fell back to the group's default state. That is the tell that your intended set_case_analysis never actually reached, or never satisfied, the mode's controlling condition.
  20. 20 How do you make PrimeTime remember the source file and line number of each exception, and what's the hard restriction?Advanced: Set `sdc_save_source_file_information` (PT) to true - its default is false - and PrimeTime records the file and line of every exception command going forward. The hard restriction is that it can only be changed before any exception has been read in; once one has, an attempt to change it errors out and the setting stays unchanged.
  21. 21 Explain why set_aocvm_table_group / read_ocvm after a timing update triggers a full update, and the flow implication.Advanced: Derating factors (multipliers applied to a cell's delay to model variation) are an input to delay calculation itself, so changing which tables apply alters delays on a broad set of arcs at once. Because arrival times propagate transitively across the whole graph, the tool can't patch just a few endpoints - it forces a full recomputation. Set all variation data before the first update.
  22. 22 How do you decide between set_driving_cell, set_drive, and set_input_transition for accurate boundary modeling?Advanced: Default to `set_driving_cell` (SDC) whenever a real library cell can represent the external driver, since it uses that cell's actual load-dependent delay model. Fall back to `set_drive` (SDC) for a driver that has no library-cell equivalent, and use `set_input_transition` (SDC) when the port's slew is genuinely load-independent, or to match another tool that only supports a fixed transition.
  23. 23 How does on-chip variation (OCV) fundamentally change the setup and hold analysis?Advanced: OCV derates parts of a path differently to build a deliberately pessimistic worst case: for setup, the data path and launch clock are treated as slow while the capture clock is treated as fast; for hold, the assignment reverses. CRPR then credits back the pessimism double-counted on the clock segment both paths share.
  24. 24 Why does a clean STA report not guarantee a working chip?Advanced: Static timing analysis (STA) only checks that data arrives inside the setup and hold windows implied by the constraints you gave it - it cannot tell you whether those constraints describe the real hardware. A report with zero setup and hold violations can still ship a broken chip if a false path hid a real one, a clock-domain crossing was never checked for metastability, or a whole cone of logic was left unconstrained and silently dropped from the count.
  25. 25 What timing checks does PrimeTime run besides setup and hold, and why can all of them pass while one is silently skipped?Advanced: Beyond the setup and hold check, PrimeTime also verifies recovery and removal times on asynchronous set/reset pins, minimum pulse width and minimum period on clocks, and design-rule limits like maximum transition and maximum capacitance. Any one of these can be skipped entirely if the object it applies to was never constrained, so a clean setup/hold report does not by itself mean every check actually ran.
  26. 26 Why can the same netlist report a different critical path before and after place-and-route?Advanced: Before place-and-route, PrimeTime estimates wire delay from a wire-load model or a rough placement guess; after routing, it uses real extracted parasitics from the actual metal geometry. Because interconnect delay - not gate delay - usually dominates at advanced nodes, a path that looked fastest on paper can become the slowest once real wire lengths and coupling are known, and a different path takes over as the critical one.
  27. 27 How do you constrain a clock divider generated by a flip-flop?Advanced: A flip-flop that toggles on every rising edge of an input clock divides that clock's frequency by two, and PrimeTime needs a `create_generated_clock` (SDC) statement at its Q output so the tool knows the new clock's period and phase instead of treating that pin as an ordinary data output. For a clock derived from the rising edge of its master, `-divide_by` is enough; for one derived from the falling edge, or with an uneven duty cycle, `-edges` gives the control `-divide_by` cannot.
  28. 28 How do you cascade multiple generated clocks from the same master clock?Advanced: When one generated clock feeds another - for example a divide-by-2 clock that is itself divided again to make a divide-by-4 clock - each stage's `create_generated_clock` (SDC) should name the immediately preceding generated clock as its `-master_clock` (SDC) and `-source`, not the original master, so PrimeTime can trace the chain edge by edge instead of guessing. Chaining the definitions this way keeps each stage's source-latency calculation limited to the logic between that stage and the one before it.
  29. 29 How do you define the generated clocks needed for a PLL with a feedback divider?Advanced: A phase-locked loop (PLL) needs its output clock declared as a generated clock with `-pll_feedback` and `-pll_output` (SDC) so PrimeTime can compute the phase correction the PLL applies between its reference and feedback pins. If a flip-flop sits on the feedback path - dividing the PLL's output frequency back down to match the reference - that flip-flop's output also needs its own generated-clock definition, because the PLL's phase correction only works once the tool can trace the entire loop, sequential elements included.
  30. 30 How do you make clock jitter automatically propagate from a master clock to every clock it generates?Advanced: The `set_clock_jitter` (SDC) command, applied to a master clock, sets the same jitter properties on every clock generated from it, so you do not have to repeat the jitter values on each generated clock individually. `report_clock_jitter` (PT) then shows the cycle jitter, duty-cycle jitter, and which master clock's jitter each generated clock inherited, so you can confirm the propagation actually took effect.
  31. 31 Why does interclock uncertainty override simple clock uncertainty when both apply to the same path?Advanced: Simple clock uncertainty describes the skew of one clock against its own ideal edges; interclock uncertainty describes the skew specifically between two named clock domains, and it is the more specific description of the two. When a path qualifies for both because its launch and capture clocks are different, PrimeTime uses the interclock value and ignores the simple one, on the assumption that a value written specifically for that pair of clocks is more accurate than a general per-clock value.
  32. 32 Why should you set clock uncertainty on the clock object instead of a clock port or pin?Advanced: Setting `set_clock_uncertainty` (SDC) on a port or pin applies it only to the capturing registers downstream of that specific object; if multiple uncertainty values reach the same clock multiplexer from different ports, PrimeTime applies the worst of them to the mux's entire fanout, even to registers clocked by an input the mux is not currently selecting. Setting the uncertainty on the clock object itself avoids that ambiguity, because the value follows the clock definition rather than one physical point in its network.
  33. 33 How do you constrain a clock produced by a pulse generator that does not change frequency?Advanced: A pulse generator that keeps the incoming clock's frequency but reshapes it into a narrow pulse can be described with the `pulse_clock` attribute instead of a full generated-clock definition, using one of four senses - `rise_triggered_high_pulse`, `rise_triggered_low_pulse`, `fall_triggered_high_pulse`, or `fall_triggered_low_pulse` - to say which master edge triggers which polarity of pulse. The actual pulse width is then set with `set_clock_latency` (SDC) rather than a waveform, because an ideal pulse-clock sense starts life with zero width by definition.
  34. 34 Why does set_multicycle_path without a matching -hold setting shift the hold check?Advanced: Because every valid hold relationship is defined relative to the setup relationship, changing the setup relationship with `set_multicycle_path -setup` (SDC) automatically moves the hold check's capture edge along with it - usually to a point that does not match what the design actually needs. The standard fix is to pair it with a second command, `set_multicycle_path (N-1) -hold ...` (SDC), that moves the hold capture edge back to where it belongs.
  35. 35 How do you tell whether a timing exception actually matched the path you intended?Advanced: `report_exceptions` (PT) lists every exception-setting command and flags each one with a letter code when part or all of it was ignored - `f` for an invalid startpoint, `t` for an invalid endpoint, `p` for a non-existent path, and `o` for a path overridden by a higher-priority exception. A command that is fully ignored does not show up in the default report at all; `report_exceptions -ignored` (PT) is what surfaces those completely silent failures.
  36. 36 How do you find out which of two conflicting timing exceptions on the same path wins?Advanced: `report_timing -exceptions dominant` (PT) reports the single exception that actually governs a specific path, and `report_timing -exceptions overridden` (PT) shows any others that were considered but lost, when more than one exception-setting command touches the same points. As a general precedence rule, `set_max_delay` (SDC) outranks `set_multicycle_path` (SDC) on the same path, so an explicit maximum-delay override wins even if a multicycle exception was written for the same through-point.
  37. 37 Why can the same set_false_path command expand differently in PrimeTime than in ICC2?Advanced: When a `set_false_path` (SDC) or similar exception command names a sequential cell in its `-from` or `-to` option, PrimeTime automatically expands that command to every clock or data pin of the cell and applies the exception pin by pin. Some other tools, including IC Compiler II, keep the exception at the cell level instead of expanding it, so the same SDC line can end up resolving overlapping or conflicting exceptions differently depending on which tool reads it.
  38. 38 How do you remove one timing exception from a path without clearing every exception on it?Advanced: `reset_path` (SDC) removes a previously-set `set_false_path`, `set_max_delay`, `set_min_delay`, or `set_multicycle_path` (SDC) exception, but only if its `-from`/`-to`/`-through` object exactly matches the object used when the exception was originally set - a near match, like a different pin on the same net, silently does nothing. Any exception-setting command also accepts a `-reset_path` (SDC) option, which clears every existing exception on the matched paths first and then applies the new one, letting you replace an exception cleanly instead of stacking a new one on top of an old one.
  39. 39 How do you read a POCV Liberty variation table?Advanced: A POCV Liberty variation table, such as an `ocv_sigma_cell_rise` (LIB) group, stores the standard deviation of a cell's delay as a function of input transition and output load, exactly the way a normal delay table stores the nominal delay itself, with a separate `sigma_type` of `early` or `late` for each direction of variation. PrimeTime looks up the sigma value for the arc's actual transition and load, then scales it by a corner multiplier - the K sigma value, 3 by default - to get the derate actually applied at each timing corner.
  40. 40 How do you enable POCV analysis in PrimeTime, and what happens when a cell has no variation data?Advanced: POCV analysis turns on with a single application variable, `set_app_var timing_pocvm_enable_analysis true` (PT), after which PrimeTime performs graph-based POCV timing updates automatically as part of every `update_timing` (PT) run; a POCV side file, if one is used instead of or alongside library-based data, is loaded separately with `read_ocvm` (PT). A cell with no variation data anywhere - no Liberty sigma tables and no side-file entry - simply gets no statistical derate on that arc, which is exactly what the diagnostic `report_ocvm -list_not_annotated` (PT) command is built to surface.
  41. 41 How does distance-based POCV derating differ from single-parameter POCV, and can the two combine?Advanced: Single-parameter POCV models each cell's own random variation independently, as a statistical distribution built from that cell's own sigma data. Distance-based POCV instead models systematic variation across a timing path as a function of the physical distance the path spans on the die, computing one scalar derate factor from a lookup table and applying it to shift the mean of the path's timing - never the standard deviation - and the two can be combined in the same analysis, since PrimeTime computes and applies each contribution independently.
  42. 42 Why can a moment-based POCV analysis report a mean that differs from the nominal delay value?Advanced: Ordinary, symmetric POCV models variation as a normal distribution, where the nominal delay and the statistical mean are the same number. Moment-based POCV instead allows an asymmetric distribution - a longer tail in one direction than the other - and once a distribution is skewed, its average value is no longer the same as the no-variation nominal value, so the library separately reports a mean shift describing exactly how far the mean has moved away from nominal.
  43. 43 How does POCV model variation in vias, and why does it need slew variation data?Advanced: Via variation models the manufacturing spread in vias - the connections between metal layers - as an independent, Gaussian random variable per via, contributing both delay and slew variation because a via carries both resistive and capacitive components. It specifically needs slew variation data from LVF libraries because a via's resistance affects how much the signal's slew degrades as it travels along the net, and that slew-degradation effect has to be computed and propagated accurately, not just its delay contribution.
  44. 44 How does a SPEF corner differ from a timing corner?Advanced: A timing corner sets the process-voltage-temperature (PVT) condition a Liberty (.lib) library was characterized at; a SPEF corner sets the resistance and capacitance values a parasitic extraction tool computed for the same layout under a stated extraction condition. Signoff needs both because delay depends on two things that vary independently: how fast a transistor switches, and how much resistance and capacitance the surrounding wire adds. Pairing them wrong -- say, a slow-process library with a best-case, low-R low-C SPEF corner -- hides real violations instead of finding them.
  45. 45 How do CCS timing and CCS noise models work together during signoff?Advanced: A CCS timing model in the Liberty (LIB) library describes how a cell's output current drives its load, so PrimeTime can compute delay and slew accurately even when interconnect resistance rivals the driver's own resistance. A CCS noise model, a separate table in the same Liberty file, describes how well a cell resists or amplifies a glitch injected by a switching neighbor. Signoff loads both because a design can pass every delay check and still fail because a quiet net glitches past its receiver's noise-immunity threshold.
  46. 46 Why does crosstalk delay analysis require separate early- and late-mode runs?Advanced: Crosstalk delay analysis checks two opposite effects on the same victim net: an aggressor switching the same direction can push the victim's edge later (delay push-out), while an aggressor switching the opposite direction can pull it earlier (delay pull-in). A setup check needs the worst push-out delay and a hold check needs the worst pull-in delay, and no single crosstalk-adjusted delay number captures both, so PrimeTime (PT) computes an early-mode and a late-mode delay for the same arc.
  47. 47 How do you decide which RC corner to use for a setup check versus a hold check?Advanced: A setup check wants the parasitic corner that maximizes total delay, so it pairs with the extraction corner with the highest resistance and coupling capacitance (often labeled a worst, or RCmax, corner). A hold check wants the corner that minimizes delay and margin, so it pairs with the lowest-resistance, lowest-capacitance corner (often labeled a best, or RCmin, corner). The two checks use opposite ends of the same extraction spread because each is trying to catch the situation where timing is least forgiving for that particular check.
  48. 48 What is an extracted timing model (ETM), and why use it for hierarchical blocks?Advanced: An extracted timing model (ETM) is a compact, black-box description of a block's input-to-output timing -- arrival times, required times, and internal delay arcs -- built once from the block's full netlist so the top-level analysis never has to re-read that netlist directly. Hierarchical designs use an ETM because loading every block's full gate-level detail at the top level makes a full-chip run too slow and too memory-heavy to iterate on, while an ETM keeps just enough timing information for the top level to check the block's boundary correctly.
  49. 49 What is a quick timing model (QTM), and how does it differ from an ETM?Advanced: A quick timing model (QTM) is a boundary timing model a designer builds by hand, from a spec or an early floorplan estimate, before a block's real netlist even exists. An extracted timing model (ETM) is instead generated automatically from a block's actual, already-implemented netlist. Teams use a QTM early in the flow, often just to hold a placeholder for top-level planning, and replace it with a real ETM once the block is designed and its true timing is known.
  50. 50 How do you decide which scenarios to merge versus keep separate in a signoff run?Advanced: Two MCMM scenarios can be merged into one report only when they share the same constraints on every path the report will show, which usually means the same mode and enough corner similarity that neither scenario's worst path is masked by the other's. Scenarios get kept separate whenever a designer needs to trace a violation back to a specific mode or corner, since a merged view can only show the worst number across whatever it combined, not which scenario produced it.
  51. 51 Why does an ETM hide internal timing arcs, and what risk does that create at the top level?Advanced: An extracted timing model (ETM) keeps only enough information at each boundary pin -- arrival time, required time, and the constraints tied to it -- to reproduce the block's external timing behavior, and deliberately drops the internal gates and nets that produced those numbers. That compression is exactly what makes the model small and fast, but it also means the top level cannot see or verify any assumption baked into the block at extraction time, so a mismatch between what the block assumed and what the top level actually presents can go undetected.
  52. 52 How does hierarchical timing analysis handle a clock that crosses a block boundary?Advanced: A clock entering a block from the top level has to be defined consistently on both sides of the boundary -- same period, same source latency assumption, same propagation state -- or the block's internal timing and the top level's view of that same clock will silently disagree. Hierarchical flows handle this by generating the block's own clock definition from the top-level clock tree information available when the block is built, then re-verifying that definition once the real top-level clock tree exists.
  53. 53 How do you read a full report_timing path report, section by section?Advanced: A full `report_timing` (PT) path report has four readable sections in order: a header naming the startpoint, endpoint, and which check it reports; an arrival-time section that adds up every delay from launch to the endpoint; a required-time section that works out the latest, or earliest, legal arrival from the capture clock; and a slack line, simply required time minus arrival time. Reading it section by section, instead of jumping straight to the slack number, is what lets a designer find which specific arc is actually eating the margin.
  54. 54 How do you use report_clock_timing to debug a clock network that looks wrong in report_timing?Advanced: `report_clock_timing` (PT) shows how a single clock propagates through its entire network -- every buffer and inverter from source to every endpoint -- separately from any one data path, which is what lets a designer isolate whether an odd number in a `report_timing` (PT) path report comes from the data logic or from the clock tree itself. Where `report_timing` shows one path's clock arrival as a single number buried inside a larger report, `report_clock_timing` shows the whole clock's latency and skew profile across all its endpoints at once.
  55. 55 What does a clock reconvergence pessimism removal line in a timing report actually mean?Advanced: A clock reconvergence pessimism removal (CRPR, sometimes shown as CPPR) line in a timing report is a correction the tool applies when the launch and capture clock paths share a common segment near the clock source -- it subtracts out the derating or variation margin double-counted on that shared portion, since the same physical wire cannot really run both faster and slower at once. It only removes pessimism from the common path; any divergent portion downstream of where the paths split still carries its own full derate on each side.
  56. 56 How do you find out which of several overlapping timing exceptions actually applied to a path?Advanced: `report_exceptions` (PT) lists every timing exception currently set, including which ones a later, higher-priority exception overrode or which were ignored entirely because a more specific exception already covered that path. Reading that report -- rather than trusting that a `set_false_path` or `set_multicycle_path` (SDC) command you wrote was applied -- is the only reliable way to confirm which exception actually reached a given path when several could plausibly match it.
  57. 57 How do you trace a slack difference between two PrimeTime runs back to its root cause?Advanced: Comparing two PrimeTime runs on the same path means comparing them section by section the way a single report is read -- same startpoint and endpoint, same check type, then the clock path, the data path, and the required-time computation one arc at a time -- until the first point where the two runs diverge. That divergence point, not the final slack difference, tells the designer whether the change came from the library, the parasitics, the constraints, or an actual netlist edit.
  58. 58 How does an ECO in PrimeTime fix a hold violation without touching placement?Advanced: A PrimeTime ECO fixes a hold violation by inserting a delay buffer or upsizing a cell on the failing path using commands like `insert_buffer` or `size_cell` (PT), choosing cells from a list of pre-placed spare cells or small legal gaps so the physical implementation tool doesn't need to re-place or re-route the design. Because hold is fixed by adding delay to the data path rather than by making anything faster, and delay-adding cells are small and local, this kind of fix can usually stay confined to the immediate site of the violation instead of disturbing the surrounding layout.
  59. 59 How does a PrimeTime ECO fix a setup violation by resizing or buffering instead of re-placing cells?Advanced: A PrimeTime setup ECO reduces delay along the failing path, usually by upsizing an undersized cell to drive its load faster or by inserting a buffer to split a long, slow net into two shorter, faster-driven segments -- both changes that `fix_eco_timing -type setup` (PT) can select automatically. This works without re-placement whenever a larger cell or an extra buffer fits into the existing site or a small nearby gap; when it doesn't fit, the ECO has to fall back to a fix that does require moving something, which is why setup fixes are less reliably placement-free than hold fixes.
  60. 60 What is the difference between a placement-only ECO and a full ECO that changes cell instances?Advanced: A placement-only ECO moves existing cells to new legal locations without changing what those cells are or how they're connected -- used for physical fixes like DRC cleanup or small routing congestion relief. A full ECO changes the netlist itself -- swapping a cell's size or type, inserting a new buffer, or rewiring a connection -- which is what a timing fix from `fix_eco_timing` (PT) actually does, and which then requires the physical tool to place and connect whatever new or changed cell the edit introduced.
  61. 61 Why does an ECO verified at one corner still need a full MCMM re-run before signoff?Advanced: A PrimeTime ECO fix is verified against the single scenario it was computed in, using estimated parasitics for anything not yet physically routed, so it only proves the fix works under that one corner and that one estimate. Signoff needs every scenario in the full MCMM matrix re-checked with the real, post-implementation parasitics, because a fix that clears the violation it targeted can create a new one elsewhere, or fail to hold once the actual routed layout -- rather than the ECO tool's estimate -- is used.
  62. 62 What is a spare cell, and why does a freeze-silicon ECO flow depend on having them pre-placed?Advanced: A spare cell is an unconnected, pre-placed standard cell -- often a simple gate or buffer -- dropped into the layout during initial placement specifically so a later ECO can wire it into the netlist without adding anything new to the physical layout. A freeze-silicon ECO flow, used when the mask set can no longer change, depends on spare cells because every fix in that flow has to reuse existing silicon rather than requiring new cells to be placed and routed from scratch.
  63. 63 How do you decide whether a timing violation needs an ECO fix or a full place-and-route re-run?Advanced: A violation is a good candidate for an ECO when it's small in magnitude, localized to a few paths, and fixable by resizing, buffering, or reconnecting a handful of cells without exceeding what spare capacity or small layout gaps can absorb. A violation calls for a full place-and-route re-run instead when it's large, widespread across many paths sharing a systemic cause -- a congested region, a poor floorplan decision, an under-resourced clock tree -- because an ECO can only patch individual paths one at a time and cannot fix the systemic condition creating many of them at once.

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