What command applies OCV/AOCV derating, and how do -early/-late and cell_delay/-net_delay/-clock/-data qualifiers change what gets derated?
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
set_timing_derate (SDC) is the command that applies OCV derate factors. Its qualifiers scope exactly what gets multiplied: -early or -late chooses shortest-path or longest-path delays, -cell_delay/-net_delay/-cell_check chooses which kind of delay component, and -clock/-data chooses which side of the path. Omitting a scoping qualifier applies the factor to everything in that early/late direction across the whole design.
Technical Explanation
set_timing_derate(SDC) always requires either-earlyor-lateโ there is no default direction, because the two directions model opposite physical assumptions (early models a fast corner for the shortest-path side of a check, late models a slow corner for the longest-path side), and applying both needs two separate commands.- Using the command at all implicitly switches the tool into on-chip variation analysis mode, equivalent to
set_operating_conditions -analysis_type on_chip_variation(SDC/PT) โ a detail worth knowing, since a strayset_timing_derateleft in a script changes the whole analysis mode, not just one number. -cell_delayand-net_delay(SDC) scope the factor to just cell delays or just net (interconnect) delays;-cell_check(SDC) scopes it to library setup/hold check margins themselves, as distinct from propagation delay through a cell.-clockand-data(SDC) scope the factor to only the clock network or only the data path, letting a designer apply a different derate to clock buffers (often built from higher-drive, more uniform cells) than to the general standard-cell data path.- Qualifiers combine:
set_timing_derate -clock -increment -late 0.10 [get_cells ...](SDC) adds an incremental late derate scoped to clock cells within a specific cell list, on top of whatever base derate already applies design-wide โ-incrementadds to rather than replaces the existing factor for that scope. - With no cell/pin/clock argument at all,
set_timing_derate -late 1.2(SDC) applies late derating to every late (longest-path) cell and net delay in the whole design; adding a qualifier and an object list narrows that scope, and more specific settings take precedence over the broader design-wide default. report_timing -derate(PT) prints the per-segment derate factor actually used for a given reported path, andreport_timing_derate(PT) reports the derate settings currently configured โ both are the way to confirm a layered set of-clock/-data/-cell_delayqualifiers resolved the way intended, rather than assuming the last command written wins.
Common Mistake
The Trap: issuing set_timing_derate -late 1.2 (SDC) alone and assuming hold is now covered too.
- Without a matching
-earlycommand, only the longest-path (setup-relevant) direction is derated; hold checks, which rely on the shortest-path (early) direction, are left at nominal delay entirely โ a design can pass a review that only checked the late-derate value and still have unverified hold margin. - Layering several scoped
set_timing_deratecommands (design-wide, then-clock-scoped, then a specific cell list) without then re-checking withreport_timing_deraterisks assuming the broadest command still applies somewhere it has actually been overridden by a narrower, later one.
Follow-up Question & Model Response
"If you need clock buffers to carry a tighter derate than the rest of the design because they come from a more uniform, high-drive cell subset, how would you set that up without breaking the design-wide setup and hold coverage?"
Candidate Model Response: I would first set the design-wide early and late derate factors that apply to all cells and nets, covering both setup and hold globally. Then I would add -clock-scoped set_timing_derate commands, again with both -early and -late, using the tighter factor appropriate to the clock buffer subset โ the clock-scoped commands narrow the derate only for clock-network cells and leave the data path at the design-wide value. I would finish by running report_timing_derate to confirm the clock-scoped values actually took effect over the broader default, since a scoping mistake here silently reverts clock cells back to the design-wide factor.
Practical Example
Worked case: a design-wide baseline is set with set_timing_derate -early 0.92 and set_timing_derate -late 1.08 (SDC), covering all cells and nets. Clock-tree cells, built from a more tightly controlled high-drive library subset, get a narrower derate with set_timing_derate -clock -early 0.96 [get_lib_cells CLKBUF] and set_timing_derate -clock -late 1.04 [get_lib_cells CLKBUF]. report_timing -derate on a path through one of those clock buffers confirms 1.04 was applied there instead of the 1.08 design-wide value, while the same report on a data-path standard cell confirms the full 1.08 still applies.
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