Level 4: Signoff Reasoning

Expert STA Interview Questions

Reason through variation, CRPR, crosstalk, MCMM, ECO flows, correlation, and defensible timing signoff.

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What to practise at this level

Reason through variation, CRPR, crosstalk, MCMM, ECO flows, correlation, and defensible timing signoff.

01 Walk through a full setup check including clock reconvergence pessimism (CRPR) — why does OCV derating create artificial pessimism on shared clock paths, and how is it removed?Expert: A setup check compares when data arrives at a flip-flop against the latest time it is allowed to arrive. On-chip variation (OCV, the assumption that identical cells on the same chip can still run at slightly different speeds) forces the tool to derate the launch clock path late and the capture clock path early, even though both paths often share the same physical wires up to some branch point. That double-counts variation on the shared segment. Clock reconvergence pessimism removal (CRPR) finds that shared segment and credits back the extra margin.
02 How does temperature inversion complicate the assumption that hold is always worst at the fast/cold corner?Expert: Cell delay normally shortens as temperature drops, because carrier mobility improves — this is why designers default to the coldest corner for hold analysis. At low supply voltage, though, delay can start increasing as temperature drops instead, because the threshold voltage's own temperature dependence takes over from mobility. This reversal is called temperature inversion, and it means the coldest corner is not automatically the fastest, or the worst, corner for hold.
03 How do you model and verify timing across multiple clock domains with different frequencies (e.g., a 2:1 frequency crossing)?Expert: A frequency-divided relationship between two clocks — say a 2:1 crossing where one domain runs at half the frequency of another — is modeled with a generated clock: a clock definition that derives its edges from a source clock using a stated divide ratio, instead of an independent `create_clock` on the same physical clock pin. That lets the tool compute the exact synchronous relationship between every edge of both clocks, rather than treating the crossing as an unrelated, asynchronous boundary.
04 What goes wrong when a compound generated clock (divide-then-gate) is defined incorrectly, and how do you validate it?Expert: A compound generated clock — one that is first divided down from a faster source clock and then gated off (stopped and started) by an enable signal — has to encode both operations correctly in its SDC. Get either one wrong, and the tool computes the wrong period, the wrong edges, or fails to recognize the derived clock's relationship to the rest of the design, since it can only reason about the exact waveform the designer describes to it.
05 What is the exact mechanism by which clock reconvergence pessimism removal (CRPR/CPPR) computes its credit?Expert: The tool walks the clock tree from its root toward the launch and capture flops and finds the last pin both paths still share — the common point. It then computes the derated delay to that pin twice: once using the derate factor the launch side would apply, once using the derate factor the capture side would apply. The difference between those two derated values is added back into the path's slack as the CRPR credit, because the shared silicon cannot actually run at two different speeds at once.
07 How does AOCV (path-depth/distance-dependent derating) reduce pessimism compared to flat OCV, with a worked numeric example?Expert: Flat OCV applies one multiplier to every cell and net delay on a path, regardless of how many stages the path has or how far it spans. Advanced on-chip variation (AOCV) instead looks up a smaller derate factor for paths with more logic stages or a shorter physical span, because random gate-to-gate variation partially cancels out over many stages, while systematic variation grows with distance. The result is a path-specific factor that is usually less pessimistic than one flat number applied everywhere.
08 How does POCV combine per-arc sigma values, and how does that scale differently than flat derating as path length grows?Expert: Parametric on-chip variation (POCV) gives each timing arc its own nominal delay and a standard deviation, or sigma, taken from the library's variation data — rather than one derate factor applied uniformly. Along a path, independent per-arc sigmas combine statistically, so total path variation grows with roughly the square root of the number of stages, not linearly with stage count the way flat derating effectively does. That makes flat derating increasingly over-conservative on long paths.
09 What command applies OCV/AOCV derating, and how do -early/-late and cell_delay/-net_delay/-clock/-data qualifiers change what gets derated?Expert: `set_timing_derate` (SDC) is the command that applies OCV derate factors. Its qualifiers scope exactly what gets multiplied: `-early` or `-late` chooses shortest-path or longest-path delays, `-cell_delay`/`-net_delay`/`-cell_check` chooses which kind of delay component, and `-clock`/`-data` chooses which side of the path. Omitting a scoping qualifier applies the factor to everything in that early/late direction across the whole design.
10 What is the exact mechanism by which crosstalk delay differs from crosstalk noise, and why does the Miller effect make an opposite-switching aggressor roughly twice as impactful as a quiet one?Expert: Crosstalk delay happens when the victim net is already switching, and a neighboring aggressor net's coupling current speeds up or slows down that transition — this shifts when the victim crosses its switching threshold, changing timing. Crosstalk noise happens when the victim is quiet, and coupling current alone produces a spurious glitch bump. The Miller effect is why an aggressor switching in the opposite direction from the victim roughly doubles the effective coupling capacitance compared to a quiet aggressor, since the voltage across the coupling capacitor changes by twice as much.
11 Why can summing every aggressor's worst-case crosstalk contribution be overly pessimistic, and what actually limits how many aggressors can realistically align?Expert: Naively adding every aggressor's individually worst-case contribution assumes all of them can switch at exactly the moment needed to maximally disturb the victim, in the worst-case direction, all at once. Two things actually constrain this: each aggressor's own timing window (the real range of times its edge can occur, given its own paths and clocks) may not even overlap the victim's transition window, and the probability that every small aggressor aligns simultaneously in the same direction drops fast as the aggressor count grows — which is why the tool can use a statistical composite-aggressor model instead of a flat worst-case sum for the smaller contributors.
12 Does PrimeTime (per the supplied PTUG) provide a command to create or schedule 'useful skew,' or is that a different tool's job — and what does PrimeTime actually give you regarding skew?Expert: PrimeTime does not include a command that creates or schedules useful skew (deliberately unbalancing clock arrival times at different flops to borrow slack from one path and give it to another). That scheduling happens upstream, during clock tree synthesis in the implementation tool. PrimeTime's role is downstream: it analyzes and reports whatever skew already exists in the clock tree, using commands like set_clock_uncertainty and report_clock_timing, rather than commands that build the skew into the tree in the first place.
13 What is the difference between set_false_path/set_max_delay and the more surgical set_disable_timing, and how does exception precedence resolve conflicts between them?Expert: set_false_path and set_max_delay are point-to-point exceptions: they remove or replace the timing requirement on specific paths but the tool still computes and can report the path's delay. set_disable_timing instead removes the arcs through a pin, cell, or port from the timing graph entirely, so no path can be traced through that point at all — more efficient when every path through a point is genuinely false. When exceptions conflict on the same path, PrimeTime resolves it per path using a fixed priority: set_false_path beats set_max_delay/set_min_delay, which beats set_multicycle_path, and a more specific -from/-to/-through specification beats a more general one.
14 What options does PrimeTime provide for filtering and reporting specific timing paths (through/from/to, nworst, path tagging), and why would you use path tagging for exhaustive PBA?Expert: report_timing offers point-based filtering with -from, -to, and multiple -through arguments (order matters — each -through is matched in sequence), count-based filtering with -nworst and -max_paths, and slack-based filtering with -slack_lesser_than. Path tagging is a separate feature: it marks a set of already-analyzed paths with a name, so a later exhaustive path-based analysis (PBA) run can skip re-analyzing paths already covered by an earlier, cheaper analysis mode, saving runtime on a technique that is otherwise expensive to run broadly.
15 What is the difference between 'union' and 'every-group' TNS computation in report_global_timing, and why does this matter for DMSA (multi-scenario) results?Expert: Total negative slack (TNS) sums up how much every violating endpoint is behind schedule. In union mode (the default), each endpoint contributes only its single worst negative slack value to the total, even if it belongs to more than one path group or scenario. In every-group mode, an endpoint contributes separately for every path group it is negative in, so the same physical flop can be counted more than once. The tool selects the mode with the timing_report_union_tns variable, and the choice changes the reported TNS magnitude significantly once distributed multi-scenario analysis (DMSA) combines several scenarios together.
16 Walk through the fix_eco_timing flow for setup versus hold, and explain why the recommended ECO fixing order matters.Expert: fix_eco_timing fixes setup violations by default using cell sizing alone, reducing data path delay without adding buffers, while it fixes hold violations using both cell sizing and buffer insertion, adding delay where a path is too fast. Setup is fixed first because it is the harder violation to repair and is allowed to introduce new hold violations along the way; hold is fixed second, and it deliberately avoids reintroducing setup or design-rule violations, since fixing hold after setup means the setup picture is already considered final.
17 What is MCMM/DMSA (multi-mode multi-corner / distributed multiscenario analysis), and what commands does PrimeTime provide to manage it?Expert: MCMM (multi-mode multi-corner) is the requirement to verify and optimize timing across every combination of a design's functional modes and its process/voltage/temperature corners, since a chip must work correctly in every mode it will actually run and at every corner silicon can land on. DMSA (distributed multiscenario analysis) is the execution architecture that makes checking all those combinations tractable: a manager process coordinates a scenario for each mode-corner combination, running each on its own worker process, then merges the results back into one signoff view.
18 What are RC corners (Cmax/Cmin/RCmax/RCmin), and why might the worst corner differ between a short capacitance-dominated net and a long resistance-dominated net?Expert: RC corners model the extremes of interconnect variation caused by manufacturing spread in wire width and spacing. Cmax pairs wider wires and tighter spacing (lower resistance, higher capacitance); Cmin pairs narrower wires and wider spacing (higher resistance, lower capacitance); RCmax and RCmin describe the analogous extremes when resistance, not capacitance, dominates delay. A short net's delay is driven mostly by capacitive loading, so Cmax tends to be its setup-worst corner; a long net's delay is driven mostly by resistive RC delay, so RCmax tends to be its setup-worst corner instead — the same physical wire extremes stress different nets differently depending on which effect actually dominates their delay.
19 What does a rigorous 'timing is clean' signoff declaration actually require, beyond a report showing zero violations?Expert: A zero-violation summary only proves that whatever paths, corners, and checks the tool actually looked at came back clean — it says nothing about paths that were never constrained, corners that were never run, or exceptions that silently swallowed real risk. A rigorous signoff declaration means working through a full checklist — every mode-corner scenario, OCV/derating settings, crosstalk analysis, exception review, and unconstrained-endpoint checks — and confirming each one was genuinely covered, not just that the final number happened to read zero.
20 An engineer says 'silicon always beats signoff, so our margins must be too conservative.' How do you respond, and what's the danger in that reasoning?Expert: Observing that a handful of measured parts consistently beat signoff timing can be a legitimate signal of recoverable over-conservatism, worth investigating carefully. But treating it as proof that margins should simply be relaxed is dangerous, because the parts an engineer typically gets to measure are the ones already close to typical process — not the worst-case-corner parts signoff margins exist specifically to protect. A design that never violates on the parts you measured says little about the parts you didn't.
21 Explain how CRPR, crosstalk, and PBA interact for an SI-critical clock path, end to end.Expert: Three layers stack on top of each other. Base CRPR removes the ordinary OCV double-count on the shared clock segment when the tool computes final slack. A second layer removes the coupling-delay pessimism CRPR would otherwise miss on that same shared segment, but only for zero-cycle checks, where the identical clock edge launches and captures. A third layer, enabled by pba_enable_xtalk_delay_ocv_pessimism_reduction, extends CRPR into the arrival-window computation itself during path-based analysis (PBA), since those windows do not get CRPR by default.
22 Explain how MIS, CRPR, and the hold check interact on a short clock-adjacent data path.Expert: Both effects change the same number — min delay, which is the value the hold check compares against the clock's arrival. Multi-input switching (MIS, a faster delay the library allows when several gate inputs switch together) shortens the data side, so data arrives earlier. Clock reconvergence pessimism removal (CRPR) adjusts the shared portion of the launch and capture clock paths. The hold check then compares the MIS-shortened arrival against the CRPR-adjusted capture time — and the two effects do not push the same way, so both need to be modeled correctly to get the true margin.
23 Walk through how trip points, slew, and the RC-011 extrapolation limit chain together into a single accuracy failure mode.Expert: Trip points (the waveform thresholds the library defines for measuring a signal's timing) set where slew gets measured. A wrong or unexpected trip point corrupts that slew value, which then indexes the driver's delay tables out of range — the tool has to extrapolate, PrimeTime's RC-011 warning, and extrapolation both loses accuracy and hands the next stage an inflated slew, feeding the same problem forward.
24 How should constraint rigor differ for a safety-critical versus a consumer design?Expert: The SDC commands and checks are the same on both. What changes is how much proof you must produce that every constraint is correct: a safety-critical design demands justified I/O timing budgets, zero-tolerance completeness checks, individually reviewed exceptions, and an auditable record of which constraint version signed off which tapeout. A consumer design runs the same methodology with lighter formal review, because the cost of a mistake is quality risk rather than a safety hazard.
25 How would you defend investment in clock methodology, tooling, and verification to an executive?Expert: Every setup and hold check in the whole signoff is measured against the clock model, so a clock mistake corrupts many paths at once and produces no distinct error message — it just looks like ordinary timing data until it fails silicon. The methodology cost is small and reused on every run; the exposure it prevents is measured in respins and schedule, so the return is heavily asymmetric.
26 Explain why set_voltage's max-delay number is the lower voltage in a corner pair, connecting it to STA fundamentals.Expert: A max-delay corner is the worst-case setup condition — the slowest the design can legally run. Lower supply voltage gives a transistor less drive current, so switching is slower and delay is larger. That is why the positional (max-delay) value in set_voltage is the lower voltage in the pair, and the -min value — the min-delay, hold-checking voltage — is the higher one.
27 A path shows negative setup slack, but you believe it's a genuine multicycle path that was never constrained. Give the end-to-end procedure to confirm and fix it safely.Expert: Treat it as an investigation, not a slack-closing shortcut. Confirm the path is real and see what already constrains it, get the real number of allowed cycles from the RTL designer, apply set_multicycle_path -setup N with the matching -hold (N-1), then re-check with report_timing -exceptions all that the exception is dominant and covers exactly this path and nothing else.
28 Construct a scenario where the back-annotation precedence order produces a subtly wrong result that passes all obvious checks.Expert: A forgotten set_resistance override on one net outranks a later, accurate SPEF read for that same net, because PrimeTime's back-annotation precedence puts lumped resistance and capacitance commands above detailed parasitics. report_annotated_parasitics -check still passes, because the net does have a complete RC network — it just is not the one everyone assumes.
29 Why does constraint variation (setup and hold sigma) need its own enable on top of POCV, and what goes wrong if you forget it?Expert: Parametric on-chip variation (POCV) models delay variation on cell and net arcs by default, but not automatically the variation of the setup and hold requirements themselves. That needs a separate enable, timing_enable_constraint_variation, plus library data in Liberty variation format (LVF). Forget it and the tool compares a distribution of arrival times against a fixed, zero-variation requirement — an inconsistent and optimistic model.
30 How would you decide which clock-related decisions to standardize versus leave to block owners?Expert: Standardize whatever must be identical everywhere it appears to compose correctly across the chip — the primary clock definitions, the clock-group relationships, the ideal-versus-propagated and uncertainty conventions, and the verification gates. Delegate whatever is genuinely internal to one block, like a local generated clock or a block-specific uncertainty refinement, as long as it follows the standardized conventions.
31 Two engineers get different slack on the same path, same corner. One used report_timing, the other report_crpr plus hand arithmetic. How do you adjudicate?Expert: report_timing is the signoff number, and the gap almost certainly comes from a merging step that only report_timing performs: it merges adjacent common-clock-path points whose reconvergence pessimism differs by less than a threshold, 5 picoseconds by default, which slightly under-credits pessimism removal. report_crpr reports the unmerged, more granular value, so hand-adding its numbers on top of a separately-run report_timing double-counts or misaligns the credit.
32 Explain the transparent-latch two-CRPR mechanism's effect on time borrowing, with the sign of each effect.Expert: A transparent latch endpoint gets two separate reconvergence pessimism values, one for the opening edge and one for the closing edge, because the two edges sit on opposite clock polarities. Opening-edge pessimism reduces how much time is available to borrow; closing-edge pessimism increases the maximum borrowing allowed. The two effects push in opposite directions and do not cancel out.
33 How should clock modeling rigor differ for a safety-critical versus a consumer design?Expert: Both designs use the same clock commands and modeling; what changes is how exhaustively completeness is verified, how conservatively margins are chosen and justified, and how traceable the clock spec is back to the fabricated design. Safety-critical work treats a clock error as a potential undetected hazard and adds evidenced gates and independent review; consumer work applies the same methodology with proportionate, lighter review.
34 Prove that MIS, done wrong (full factor with no window check), can be either safe-but-costly or actually wrong - and state which.Expert: Applying the full multi-input switching (MIS) speed-up factor unconditionally, with the arrival-window overlap check disabled, is the optimistic extreme for hold — MIS shortens min delay, so removing the check that limits when the speed-up applies can make data arrive earlier than the model shows and hide a real hold violation. It trades accuracy for runtime, and the accuracy it gives up is on the unsafe side.
35 A team proposes reducing the signoff corner set to save runtime near a deadline. How do you respond?Expert: Support reduction only where it is provably safe — merging modes whose constraints are genuinely compatible, or distributing the existing scenario set to run in parallel — never by silently dropping a corner. Each mode-and-corner scenario represents a real operating condition; blindly removing one means whatever path is worst-case there is simply never checked, with no signoff warning that anything was skipped.
36 A path fails hold only after you enabled crosstalk analysis. Could CRPR be involved, and how would you investigate?Expert: Possibly. Crosstalk-induced delay change on the shared segment of the launch and capture clock paths is only pessimistic — and only removable by CRPR — for a zero-cycle check, where the same clock edge launches and captures. The discriminator is whether this specific check is zero-cycle; if it is not, the crosstalk effect on launch and capture cannot be assumed identical, and CRPR correctly leaves it alone.
37 How would you decide which flow decisions to standardize organization-wide versus leave to team/project discretion?Expert: Standardize whatever must be consistent, correct, and comparable across the organization — the flow structure, the mandatory validation gates, reproducibility controls, sign-off criteria, and result format. Delegate genuinely project-specific configuration — the mode-and-corner matrix, library versions, design-specific exceptions, and debugging approach — inside that standardized framework.
38 How would you influence upstream teams (RTL, synthesis, library) to improve design-data quality for PrimeTime?Expert: Push the library team toward accurate, correctly-versioned characterization with the node's real models; the synthesis team toward a clean, linkable netlist and a shared constraint source; the RTL team toward clean, documented clocking; and establish shared naming and versioning conventions plus a fast feedback loop so a defect is reported and fixed at its source, not patched downstream on every run.
39 Explain, at the edge level, why a simultaneous source edge is not counted as the launch edge in the different-clock setup analysis, and why that's conservative-correct.Expert: For a capture edge at time t, the tool pairs it with the nearest launch edge strictly before t — never the edge at exactly t itself — because data launched at the same instant it is captured would need zero propagation delay through real logic, which is physically impossible. Reaching back to the previous edge gives a smaller available window and therefore the more restrictive, correct setup requirement.
40 Explain why the SDF PORT construct and multidrive alignment are both about clock networks, yet solve different problems.Expert: Both features exist because a clock mesh or spine has huge numbers of nearly identical nets, but they solve different problems. The PORT construct, enabled with sdf_enable_port_construct, shrinks SDF file size by collapsing near-identical INTERCONNECT delays into one PORT statement. Multidrive alignment, enabled with sdf_align_multi_drive_cell_arcs, forces one worst-case delay onto parallel driver cell arcs so a downstream simulator does not fail on ambiguous multidriven timing — and unlike the PORT construct, it is deliberately pessimistic.
41 Why can clock uncertainty, OCV derating, and CRPR all apply to the same path at once, and how does that stack into a hidden pessimism budget?Expert: A single path can carry clock uncertainty margin, an OCV derate percentage, and a CRPR credit all at the same time, because each one models a different source of variation and the tool applies them independently. Stacked together they can consume far more margin than any one term suggests, which is why a path that looks comfortably positive on a naive hand calculation can still fail in the signoff report. Reading a slack number without knowing which margins are baked into it is the real risk, not any single margin being "too conservative."
42 Why might the path PrimeTime reports as having the worst slack not be the path that is actually limiting how fast your clock can run?Expert: The tool ranks slack separately inside each path group, so the single worst number it prints is the worst slack in whichever group you are looking at, not necessarily the tightest path in the whole design. A path with a false path or multicycle exception removed from consideration, or one sitting in a different, less-scrutinized group, can be the real limiter on maximum frequency while the reported "critical path" belongs to a group with an easier bar. Trusting one worst-slack number without checking group membership and coverage across every group can hide the actual bottleneck.
43 What happens if you forget to run set_propagated_clock, and why can an ideal clock network hide a real skew problem?Expert: Without `set_propagated_clock` (SDC), the tool times every clock path as an ideal network with only the latency and uncertainty values a designer supplied, so it never sees the real, branch-by-branch skew that clock tree synthesis introduces. A path that looks comfortably positive under the ideal-clock assumption can flip to a violation the moment real, propagated clock latency is applied, because the ideal model was silently optimistic about how well-aligned the launch and capture clock edges really are.
44 How does the -pll_shift option of set_clock_latency model PLL drift and jitter differently from an ordinary fixed source-latency override?Expert: A normal `set_clock_latency` (SDC) value replaces the clock's computed source latency outright, but the `-pll_shift` option adds its value on top of whatever base latency the tool already derived for a PLL-generated clock. That distinction lets a designer layer a PLL's drift and jitter numbers onto the real, feedback-computed latency instead of overwriting it, which is the only way to keep a PLL feedback loop's timing internally consistent.
45 How do you specify a pulse clock with create_generated_clock -edges, and why does the position of the repeated edge digit change what pulse gets modeled?Expert: A pulse clock — a signal that produces a narrow high or low pulse from each edge of a source clock — is defined with `create_generated_clock -edges {n1 n2 n3}` (SDC), where the three numbers name which edges of the source clock trigger the pulse's rise, its peak, and its fall. Repeating one of those edge numbers is what tells the tool "this is a pulse," and which edge number is repeated, and where in the list it repeats, determines whether the pulse is active-high or active-low and whether it is triggered from the source's rising or falling edge.
46 Why must a cascaded chain of divide-by generated clocks name the previous generated clock as its master, instead of all pointing back at the original clock?Expert: Each stage of a divider chain — divide-by-2, then divide-by-4, and so on — needs its `-master_clock` (SDC) reference to be the generated clock immediately upstream of it, not the original source clock, because the tool derives a generated clock's waveform by tracing the real logic between it and its named master. Naming the original clock as master for every stage asks the tool to trace through logic already assigned to a different clock domain, which it cannot do, and the result is an unexpanded generated clock that PrimeTime cannot time correctly.
47 How do you use report_clock_timing to confirm a generated clock's source and network latency were computed correctly after fixing its definition?Expert: `report_clock_timing -type latency` (PT) prints, per clock pin, the transition, source latency, network latency, and total latency the tool actually computed, which is the direct way to confirm a generated clock expanded correctly instead of just trusting that the SDC no longer throws an error. A generated clock that traces properly shows a real, non-zero source latency inherited from its master and a network latency consistent with its position in the clock tree; one that still has a tracing problem shows a zero, missing, or clearly wrong latency value even when the SDC itself no longer reports an error.
48 How do -through points combine across multiple set_false_path commands, and why is that different from listing several -through points in one command?Expert: Every `-through` point inside a single `set_false_path` (SDC) command must be crossed, in the order given, for that command to match a path — it behaves like an AND across the list. Two separate `set_false_path` commands, each with its own `-through` point, instead act like an OR: a path is false if it matches either command's full requirement, not only if it satisfies both commands' through-points together.
49 When set_false_path, set_max_delay, and set_multicycle_path all match the same path, what order of priority decides which one PrimeTime actually applies?Expert: PrimeTime applies exception precedence independently to each path, not each command, and among conflicting exception types the fixed order is `set_false_path` first, then `set_max_delay`/`set_min_delay`, then `set_multicycle_path` last. When two or more of these types genuinely conflict on the same path, only the highest-ranked one takes effect and the others are silently ignored for that path.
50 Why does a more specific -from pin -to pin exception override a more general -from clock exception, even if the general one was written into the SDC first?Expert: Path specification priority in PrimeTime is based entirely on how specific the object types named in `-from`/`-to`/`-through` are, not on the order the commands appear in the SDC file. A command naming exact pins ranks above one naming a clock, so the pin-level command wins on any path both commands touch, regardless of which line was written earlier.
51 How do you find every timing exception in a design that PrimeTime silently ignored because a higher-priority exception overrode it on the same path?Expert: `report_exceptions -ignored` (PT) lists every exception command the tool computed but did not apply, because a higher-priority exception — by type or by specificity — already governed that path. Running it across the whole design after every exception file is loaded is the only systematic way to catch an exception that was accepted by the SDC parser but never actually took effect on any path.
52 Why does PrimeTime not propagate a set_case_analysis constant through a flip-flop by default, and how do you turn that on for specific cells?Expert: A logic constant set with `set_case_analysis` (SDC) propagates automatically through combinational gates, but the tool stops it at a flip-flop's output by default, because a sequential cell's output value depends on its stored state and clock behavior, not purely on its input value the way a combinational gate's output does. Overriding that default — for the whole design with a variable, or for specific cells with `set_case_sequential_propagation` (PT) — is a deliberate, narrow decision, not something to switch on globally without checking each cell it affects.
53 Why can CRPR (clock reconvergence pessimism removal) actually make a hold violation worse, rather than better, on some paths?Expert: CRPR only gives back derate on the portion of the clock tree that the launch and capture paths genuinely share in common — it never touches derate applied to the parts of the tree that diverge. On a path where the divergent branch is where the real timing risk sits, removing pessimism from the shared trunk does nothing to help that risk, while the tool still fully derates the divergent branch in the pessimistic direction, so the net effect on hold slack can be negative rather than positive.
54 Why does PrimeTime treat every output of a multi-output PLL as having the same phase when computing clock reconvergence pessimism removal, even though they don't share a physical common pin near the flops?Expert: A PLL's multiple outputs are all locked to the same reference and, by construction, meant to stay in phase with each other, so PrimeTime models them as indistinguishable for CRPR purposes even though their last shared physical pin is deep inside the PLL, far from the launch and capture flops. Removing pessimism up to that reference point is essential, because treating the outputs as independently variable would invent skew between two clocks that the PLL's own design guarantees stay aligned.
55 How does LVF (Liberty Variation Format) distance-based derating let a library model POCV variation without needing a separate AOCV side file?Expert: LVF lets a cell's own Liberty timing arcs carry distance-based derating factors directly in the library, alongside the ordinary POCV sigma tables, so the tool can look up a derate that depends on how far apart two timing points are in the clock network without loading a separate AOCV side file at all. Because the data lives in the library and can vary with slew and load like any other LVF table, it is functionally equivalent to a side file's distance-based table, but automatically tied to the cell characterization it came from.
56 Why doesn't an ordinary set_timing_derate percentage automatically scale AOCV or POCV sigma values, and what option turns that behavior on?Expert: By default, `set_timing_derate` (PT) affects only ordinary, flat cell and net delays — it does not touch the separate statistical models AOCV and POCV use, because those models already carry their own, more detailed variation data and blending in a flat percentage on top would double up two different representations of the same physical variation. The `-aocvm_guardband`, `-pocvm_guardband`, and `-pocvm_coefficient_scale_factor` options exist specifically to adjust the AOCV or POCV models themselves, separately from the ordinary derate command's default scope.
57 How do you debug a crosstalk-induced hold failure that only appears post-route?Expert: A hold failure that only shows up after routing, and not before, usually means crosstalk delay is pulling in (speeding up) the data path or the clock path once real coupling capacitance exists between physical wires. The debug approach is to re-run with signal integrity analysis on, find which net actually moved the arrival time, and confirm the aggressor and victim really switch inside the same timing window. The fix targets the coupling itself, not the derate margin.
58 Why does enabling SI analysis create new PBA-worthy paths that GBA alone never flagged?Expert: Turning on signal integrity (SI) analysis adds a crosstalk delay margin to every net PrimeTime believes could be an aggressor or victim, and graph-based analysis (GBA) applies that margin using a bounded worst-case switching window rather than a path's real timing. That extra, pessimistic margin can push previously comfortable paths close enough to zero slack that they now need a path-based (PBA) re-check to confirm whether the violation is real.
59 How do you pick RC extraction corners for crosstalk signoff when the aggressor and victim need opposite worst cases?Expert: A single RC extraction corner cannot represent worst-case crosstalk on both sides of the same coupling event, because the aggressor needs a fast edge while the victim needs to look slow and easily disturbed. Signoff handles this by extracting the same physical nets under different assumptions for the aggressor and the victim inside one crosstalk check, rather than picking one corner for the whole design.
60 How does a receiver's noise immunity curve decide whether a crosstalk glitch becomes a functional failure?Expert: A crosstalk glitch on a quiet net is only a real problem if the receiving gate is weak enough to be fooled by it, and Liberty's CCS noise (composite current source noise, a table format capturing how a cell's output responds to a disturbance) tables define exactly how much glitch height and width a given receiver can absorb before it forwards a wrong value. PrimeTime compares the actual glitch it calculates on the victim net against that receiver-specific immunity curve, not against one flat voltage threshold.
61 How do you budget timing across a hierarchical partition?Expert: Budgeting means splitting a top-level path's available time among the blocks it passes through, before every block has its own final implementation, so each block team knows its own setup and hold targets. Because the total time on a path is fixed, giving one block extra margin necessarily takes margin away from another block on the same path, so budgeting is a negotiation over a shared, limited resource, not just a per-block guess.
62 What HyperScale block context must you refresh before top-level signoff, and what happens if you don't?Expert: HyperScale, a hierarchical timing method that analyzes a block using a compact model instead of its full netlist, relies on a block context: boundary loads, arrival times, and derating assumptions taken from the top-level environment when the block model was built. If the top level changes after that snapshot, for example the floorplan shifts or a neighboring block's clock tree changes, the block context goes stale, and signoff run against it can pass on paper while the real chip does not.
63 How do you reconcile a bottom-up block's budgeted constraints against the top level's flat timing run?Expert: A block closed bottom-up against budgeted constraints, assumed boundary timing rather than real top-level values, needs to be checked against a flat, full-chip run once the top level exists, because the budget was always an estimate. Reconciliation compares the block's assumed boundary arrival and required times to what the flat run actually computes at those same pins, and treats any gap as a signal that the budget, the block, or both need another pass.
64 Why can a block that passes clean standalone still fail once its ETM is integrated at the top level?Expert: A block's standalone signoff only checks timing against the boundary assumptions used to build its extracted timing model (ETM, a compact stand-in for the block's internal timing used at the top level), not against the real conditions the top level ends up creating. If the top level's actual clock arrival, skew, or loading at the block's boundary differs from what the standalone run assumed, the same block that passed on its own can produce a failing path once its ETM is stitched into the full-chip analysis.
65 What does a PrimeTime message about an unconstrained endpoint mean, and how do you find it?Expert: An unconstrained endpoint is a register, port, or latch input with no required time defined for it, so PrimeTime cannot check setup or hold there at all; it is not a passing path, it is simply not being checked. Finding it means turning on unconstrained-path reporting with the `timing_report_unconstrained_paths` variable (PT) and running `check_timing` (PT) or `report_timing -exceptions all` (PT), which lists the endpoint and states why it has no required time.
66 Why does report_timing -exceptions dominant show a different exception than the one you actually wrote?Expert: When two timing exceptions apply to overlapping parts of the same path, PrimeTime enforces only one of them, the dominant one, based on a fixed priority order, not the order they were written in the SDC. `report_timing -exceptions dominant` (PT) shows which exception actually won, which can be a `set_max_delay` (SDC) or `set_false_path` (SDC) command instead of the `set_multicycle_path` (SDC) you may have written for that same path, if a higher-priority exception also touches it.
67 How do you script a custom timing triage list with get_timing_paths when report_timing only shows one path at a time?Expert: `report_timing` (PT) prints a fixed, human-readable report of one or a few paths at a time, which does not scale to triaging hundreds of near-critical paths after a big netlist change. `get_timing_paths` (PT) instead returns a collection of path objects that a script can filter, sort, and summarize programmatically, which is the tool built for large-scale triage rather than one path at a time.
68 How do you use report_analysis_coverage to prove every endpoint was checked across a multi-scenario signoff run?Expert: `report_analysis_coverage` (PT) reports how many endpoints were actually tested for each check type, setup, hold, and design rule checks, against how many exist in the design, which is the direct way to prove a signoff run covered everything rather than inferring it from a clean slack summary. In a multi-scenario run, several mode and corner combinations analyzed together, the merged version of this report rolls that same coverage question up across every scenario at once.
69 You inherited a design with 3,000 hold violations two days before tapeout — what is your triage order?Expert: With that little time, the priority is grouping violations by root cause before fixing anything, because 3,000 individual violations are rarely 3,000 independent problems; most trace back to a handful of systematic causes like one under-sized clock buffer stage or one derate setting. Fix the highest-leverage systematic cause first, re-run incrementally to see how many violations that single fix clears, then triage what remains, rather than working the list top to bottom.
70 When does a timing ECO cell swap in PrimeTime still require a full place-and-route pass before signoff?Expert: A cell swap that fits in the same physical footprint and existing routing can often be verified with PrimeTime's incremental timing update alone. But a swap that changes the cell's size, pin locations, or drive strength enough to need new placement legality or different routing invalidates the parasitics PrimeTime is using, so timing needs to be re-extracted, and sometimes re-routed, before signoff can trust the result.

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