What are library-definition problems or UPF-to-library mismatches, and what command reconciles a cell's actual power pins with UPF's abstract model?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
UPF talks about supply sets and strategies, while the library describes real PG pins, pin types and related-power attributes; a mismatch means the tool cannot connect one to the other. There is no single reconcile command: the Liberty PG attributes decide most of it, and for macro and top-level ports you override them with set_port_attributes -receiver_supply (UPF), its -driver_supply twin, or set_related_supply_net (UPF). report_mv_lib_cells and check_mv_design (ICC2) show where the two views disagree.
Technical Explanation
- PG pin type: Liberty marks each PG pin primary_power, backup_power and so on; a wrong type makes a dual-rail cell look single-rail.
- Related power pin: each signal pin names the PG pin that powers it; a wrong value gives the pin the wrong supply and false crossings.
- Unmapped cells: a strategy that maps to a cell outside the target library leaves GTECH cells behind;
analyze_mv_feasibility -level_shifter -format html(ICC2) lists level-shifter failure reasons. - Macro ports: for a hard macro input,
-receiver_supplybeatsset_related_supply_net(UPF), which beats the Liberty related_power_port. - Supply voltage: every supply net needs an operating voltage, or ICC2 issues UPF-057;
check_mv_design -pg_netlist(ICC2) confirms it. - Wrong file:
map_retention_clamp_cell(ICC2) is not a UPF command, so placing it inside the UPF makesload_upf(ICC2) error.
# [UPF] design.upf
set_port_attributes -ports {U_SRAM/CE} -receiver_supply SS_AON
# [ICC2] icc2_shell
report_mv_lib_cells -verbose
check_mv_design -pg_netlist
check_mv_design -pg_pin
analyze_mv_feasibility -level_shifter -format htmlWhat To Check
- report_mv_lib_cells shows the expected PG_TYPE for every power-management cell.
- Enable and data pins of isolation cells relate to the PG pins you expect.
- Every strategy maps to a usable cell in the target library.
- Hard-macro ports carry an explicit receiver or driver supply where Liberty is silent.
Command Checks & Actions
set_port_attributes -ports {U_SRAM/CE} -receiver_supply SS_AONOverride the supply of a macro input the library cannot resolve
report_mv_lib_cells -verbosePrint PG pins, PG types and related power pins per cell
check_mv_design -pg_netlistConfirm every supply net has an operating voltage
check_mv_design -pg_pinCheck the rules on PG pin connections
analyze_mv_feasibility -level_shifter -format htmlExplain why level-shifter strategies failed to map
Healthy, Suspicious & Hard-stop Results
- Healthy (illustrative): All 14 multivoltage library cells report the expected PG types, and
check_mv_design-pg_pin shows no errors. - Suspicious (illustrative): A dual-rail buffer reports only a primary_power pin, so the tool treats it as single-rail.
- Hard stop: UPF-057 on a supply net, or load_upf stops on a command it does not recognise.
Common Mistake
The Trap: Copying an old script that forces a pin-to-supply link with a related-power option no guide documents, instead of the verified port attributes.
- The UPF fails to load, and the real override,
set_port_attributes -receiver_supply(UPF), never gets applied. - Worse, someone deletes the line to get past the error, and the macro input silently falls back to whatever Liberty says.
What The Interviewer Is Testing
- Do you separate library data problems from UPF problems?
- Do you know the port-supply priority order for hard macros?
Follow-up Question & Model Response
"A hard macro has no related_power_port on one input. What does the tool assume?"
Candidate Model Response: It walks the priority list for hard-macro inputs. First comes -receiver_supply on the HighConn side, then set_related_supply_net (UPF) there, then the Liberty related_power_port. With none of them present, the input has no defined receiving supply, so crossing checks cannot judge it. Add the receiver supply in the UPF instead of hoping the domain primary is right.
Practical Example
Design Scenario: (illustrative) U_SRAM in PD_CPU (VDD0p9) has chip-enable CE, driven by U_PC in PD_MYCHIP at 1.0 V. Liberty gives CE no related_power_port, so the tool has no receiver supply for it and check_mv_design (ICC2) cannot judge the U_PC to CE crossing. The macro datasheet puts CE on its 1.0 V always-on periphery rail. Adding set_port_attributes -ports {U_SRAM/CE} -receiver_supply SS_AON (UPF) makes the crossing 1.0 V AO to 1.0 V AO, so no isolation or level shifter is needed and the check clears. Cell and pin names are illustrative.
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