Level 4: Signoff Reasoning

Expert Low Power Interview Questions

Reason through multivoltage architecture, strategy precedence, feasibility checks, library mismatches, physical implementation, and signoff.

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Reason through multivoltage architecture, strategy precedence, feasibility checks, library mismatches, physical implementation, and signoff.

  1. 01 Walk through the complete "Mychip" multivoltage architecture: what are its power domains, and how do they relate to each other?Expert: MYCHIP has four power domains: the always-on top PD_MYCHIP on VDD1p0 (1.0 V), an always-on PD_CPU on VDD0p9 (0.9 V), a switchable PD_COP on VDD1p0_SW with retention, and PD_DSP on an external rail VDDdsp that moves between 1.1 V and 0.9 V. The power controller U_PC sits in PD_MYCHIP, drives PSE, ISE and SRE, and reads PSE_ACK back from the PD_COP switch. Every crossing then needs its own strategy: a level shifter where voltages differ, isolation where the driver can be off while the receiver is on.
  2. 02 How is hierarchical UPF constructed for nested power domains, and what does create_composite_domain do?Expert: Each block carries its own UPF, and the top UPF loads it into the block instance with `load_upf -scope` (UPF), then drives the block supply ports from top nets. Top-down, ICC2 cuts the chip intent into block UPFs with `split_constraints` (ICC2); bottom-up, finished blocks come back as ETMs or macros whose port supplies you describe from outside. `create_composite_domain -subdomains` (UPF) only groups existing domains into one container, and a strategy written on it applies to each subdomain; tool support varies by release.
  3. 03 How does UPF define power-domain scope and extent, and what do the -applies_to_boundary options (upper/both/lower) control?Expert: Scope is the instance where you create a domain, and extent is the set of instances that belong to it. One instance can be the scope of several domains but sits in the extent of only one. `-applies_to_boundary` (UPF) on an isolation or level-shifter strategy picks which edge it covers: the upper boundary facing the parent, the lower boundary facing a nested child domain, or both.
  4. 04 What does a TOP-level power-intent structure look like, using the Mychip example as a reference?Expert: A top-level UPF runs in a fixed order: domains, then supply ports and nets, then each domain primary supply, then switches and strategies, and last the power states. In MYCHIP that means four `create_power_domain` (UPF) calls, VDD1p0, VDD0p9, VDDdsp and VSS shared into subdomains with `-reuse`, a switch that makes VDD1p0_SW for PD_COP, and a table of legal rail combinations. Each section may only refer to objects an earlier section created.
  5. 05 What are supply-set relationships, and what does the -resolve option of create_supply_net control?Expert: Supply sets are related when they resolve to the same nets, which you declare with `associate_supply_set` (UPF). `-resolve` on `create_supply_net` (UPF) decides the state and voltage of a net that has more than one supply source. The default, unresolved, allows one source only, so a net fed by two switches needs one_hot, parallel, parallel_one_hot or a named resolution function.
  6. 06 How does UPF represent illegal power states, and what mechanisms exist to declare them?Expert: Modern UPF marks a named state illegal with `-illegal` in `add_power_state` (UPF), and `-complete` declares that any state not defined is illegal too. Legacy PST flows declare illegal combinations by omission: any combination missing from the `add_pst_state` (UPF) rows is not allowed. Implementation reads the legal set to decide where isolation and level shifters go, so a wrong illegal state quietly removes protection.
  7. 07 How does a power switch's control and acknowledgment signal pair work?Expert: The controller drives the switch control input, and the switch chain returns an acknowledge once its last cell has turned on. The ack tells the controller the virtual rail is really up, so restore and isolation release happen only after it arrives. In UPF you declare the pair with `-control_port` and `-ack_port` on `create_power_switch` (UPF).
  8. 08 What is the architectural difference between header and footer power switches, and when would each be used?Expert: A header is a PMOS switch between the real VDD and the block virtual VDD; a footer is an NMOS switch between the block virtual VSS and the real VSS. Footers are smaller for the same on-resistance because NMOS carries more current per width, but headers keep one shared ground, which multi-voltage designs depend on. Most SoCs pick headers, and the library declares either kind with `define_power_switch_cell` (UPF).
  9. 09 How does a virtual rail behave differently from a primary rail inside a shutdown domain, using the Mychip PD_COP example?Expert: Inside PD_COP the cells run on VDD1p0_SW, a virtual rail that exists only while the header switches conduct, while VDD1p0 outside stays flat at 1.0 V. When the switches open, VDD1p0_SW decays slowly as leakage drains it and internal nodes float, and even when on it sits below VDD1p0 by the switch IR drop. Isolation, retention and always-on cells in PD_COP must therefore tap VDD1p0, never the virtual rail.
  10. 10 What is retention supply architecture, and what does -retention_supply / -use_retention_as_primary control?Expert: A retention flop keeps its normal-mode logic on the switched primary, VDD1p0_SW, and its shadow latch on an always-on retention supply, VDD1p0. You name that supply with `-retention_supply` on `set_retention` (UPF), or with the legacy net options. `-use_retention_as_primary` (UPF) goes further: the register and its output run from the retention supply, which changes the driver supply that isolation and level-shifter strategies see.
  11. 11 What is the precedence order for isolation strategies when multiple strategies could apply to the same element?Expert: When two isolation strategies could claim the same port, ICC2 ranks them in a fixed seven-level order, highest first: ports named in `-elements`, ports implied by an instance in `-elements`, ports implied by the domain name alone, `-no_isolation`, `-source` with `-sink` (both beats one), `-diff_supply_only` true, and `-diff_supply_only` false. The order of execution does not matter. If two strategies still conflict, the one created first keeps the port and later ones lose it.
  12. 12 What are the advanced level-shifter placement strategies (self/parent/fanout/automatic/sibling), and how do you choose?Expert: The ICC2 MV UG documents automatic, self, parent and other as `-location` values for `set_level_shifter` (UPF), and IEEE 1801-2015 also lists fanout; there is no sibling value in either. `-rule` and `-threshold` decide which crossings a strategy covers, and when strategies overlap ICC2 ranks `-elements` (port over instance over domain) first, then `-no_shift`, then `-source` or `-sink`, then the rest. Choose the location where both supplies are available and the fanout stays cheap.
  13. 13 How is an always-on control network constructed, and what is the automatic inference rule for always-on cells?Expert: Always-on logic is whatever must keep working inside a shutdown domain: retention cells, isolation cells, and the save, restore and isolation-enable paths that reach them. ICC2 builds it automatically, but only if the target library has always-on buffers and inverters marked with the `always_on` attribute. It then marks as always-on logic any buffer, inverter or tie cell whose supply differs from the primary supply of the domain it sits in.
  14. 14 Walk through the "smart-derive isolation strategy" gotcha for newly punched control ports: what goes wrong and how is it fixed?Expert: When ICC2 punches new hierarchical ports for retention, switch or isolation control nets, it derives a `-no_isolation` strategy on them so existing strategies do not grab them. If the control driver can be off while the port receiver is on, that becomes an isolation violation you cannot fix with your own strategies. Setting `mv.cells.smart_derive_iso_strategy_on_new_control_ports` (ICC2) to true makes the tool check the PST first and derive `-no_isolation` only where there is no violation.
  15. 15 How does analyze_mv_feasibility detect CLP-style violations when power management cells cannot be mapped to library cells?Expert: `analyze_mv_feasibility` (ICC2) is a static low-power check that asks whether every isolation, enable-level-shifter, retention and level-shifter strategy can be mapped to a real library cell. If one cannot, it issues UPF-909, returns a Tcl status of 0, and lists each failing element with the check that failed, such as a data inversion or PVT mismatch. Run it after `load_upf` (ICC2) and before implementation, and add `-level_shifter -format html` for the detailed shifter report.
  16. 16 What happens if an isolation cell has the wrong clamp value, and how would this surface during verification?Expert: The clamp value is what the always-on receiver sees while the source domain is off, so it must be the inactive level of that signal: 0 for an active-high enable, 1 for an active-low reset. Get it wrong and the receiver acts on a fake event as soon as isolation turns on, such as starting a DMA or resetting a block. Power-aware simulation shows it as a spurious event at shutdown, and static checks catch it only when the intended clamp is written down with `set_port_attributes -clamp_value` (UPF).
  17. 17 What happens if a retention strategy is given the wrong retention supply, and what UPF mechanism helps prevent this?Expert: If `-retention_supply` (UPF) points at a switched supply such as VDD1p0_SW, the shadow latches die with the domain and every retained value is lost at shutdown. Nothing fails until wake-up, when restore loads garbage. UPF helps in two ways: in implementation a missing retention supply is an error, and in simulation the default RET_SUP_COR semantics corrupt the register whenever its retention supply is off, so the bug shows up as X.
  18. 18 What happens if save/restore signals have incorrect polarity, and what UPF assertion mechanism catches this?Expert: If the sense you declare in `-save_signal` or `-restore_signal` (UPF) does not match how the power controller drives the pin, the retention flop saves at the wrong edge or restores at the wrong time, and the domain wakes up with stale or corrupt state. No option inside `set_retention` (UPF) checks polarity during implementation. You catch it with a mutex checker attached by `bind_checker` (UPF) in power-aware simulation, backed by VC LP static checks.
  19. 19 What are library-definition problems or UPF-to-library mismatches, and what command reconciles a cell's actual power pins with UPF's abstract model?Expert: UPF talks about supply sets and strategies, while the library describes real PG pins, pin types and related-power attributes; a mismatch means the tool cannot connect one to the other. There is no single reconcile command: the Liberty PG attributes decide most of it, and for macro and top-level ports you override them with `set_port_attributes -receiver_supply` (UPF), its `-driver_supply` twin, or `set_related_supply_net` (UPF). `report_mv_lib_cells` and `check_mv_design` (ICC2) show where the two views disagree.
  20. 20 What does physical implementation and signoff look like for a multivoltage design (secondary PG placement constraints, check_mv_design, Early Data Check policies)?Expert: You load the UPF, insert and check the power-management cells, build voltage areas, switches and secondary PG, then place, clock and route with the MV rules on, and re-run `check_mv_design` (ICC2) after every step. Signoff closes timing in PrimeTime against the same UPF and checks wake-up current and IR drop in RedHawk. The Early Data Check Manager decides which data problems stop the flow and which the tool tolerates or repairs.
  21. 21 What is power-state-table (PST) state explosion, and how does it constrain how many independently-switchable domains a real design can have?Expert: Every independent supply multiplies the number of possible system states, so N supplies with k states each give k to the power N combinations. Tools, verification and your own review all scale with that number, which is why real designs declare only the handful of states the product uses and mark the rest illegal. It also pushes architects to tie domains together so they switch as a group instead of independently.
  22. 22 How do you size a MTCMOS sleep transistor (header/footer), and what happens if it's undersized or oversized?Expert: Size the switch bank so its combined on-resistance, times the peak current of the domain, stays inside the IR-drop budget of the virtual rail. That sets a minimum switch count; the upper limit comes from area, the switches own off-state leakage and wake-up rush current. Undersize it and every path in the domain runs slow; oversize it and you pay leakage, area and a larger in-rush spike.
  23. 23 What is Dynamic Voltage and Threshold Scaling (DVTS / Vth-hopping), and how does it combine two leakage/performance levers at once?Expert: DVTS changes the supply voltage and the transistor threshold together at run time: VDD through the regulator, Vt through body bias on the wells. At a low-performance point it lowers VDD and applies reverse bias to raise Vt and cut leakage; at a high-performance point it raises VDD and applies forward bias to lower Vt for extra speed. DVFS alone moves only one of those two levers, so at low speed it still pays the full leakage of a fixed, fast Vt.
  24. 24 What is the rush-current problem during power-up, and how do daisy-chain vs. parallel switch-enable sequencing strategies address it?Expert: When a switched domain wakes, its whole capacitance charges from 0 V through the switches, and if they all turn on at once the charging current spikes far above normal load. That spike pulls down the shared always-on supply and can upset neighbours, including the controller doing the wake-up. Daisy-chaining the switch enables spreads the turn-on over time, trading a longer wake-up for a much lower peak.
  25. 25 How do you floorplan a switchable voltage area so IR drop and wake-up both work?Expert: Put the voltage area close to its supply bumps, spread the switches evenly under the always-on straps so every region of the block has a short path to one, and reserve an always-on channel for the cells that must stay alive. Then check static and dynamic IR on both the real and switched rails, and ramp-up current for the chosen enable order. Switch count sets IR drop; switch enable order sets wake-up time and in-rush.
  26. 26 Level shifters or isolation cells landed in the wrong voltage area. How do you debug it?Expert: The strategy `-location` decides which domain a cell belongs to, and the domain decides which voltage area it may be placed in, so a cell in the wrong VA is almost always a location or domain problem, not a placer bug. Start from `check_mv_design` (ICC2), then trace the cell with `report_mv_path -cell` (ICC2) to see its strategy, supplies and domain. Fix the strategy or make the missing supply available, then re-insert rather than hand-moving the cell.
  27. 27 An always-on buffer ended up powered from the switched rail. How do you find it and fix it?Expert: Power-aware simulation shows an always-on signal going to X when the domain shuts down, and `check_mv_design` (ICC2) reports an isolation violation on its buffer tree, because the buffer supply is less always-on than its loads. `fix_mv_design -buffer` (ICC2) repairs it, either by swapping to a dual-rail buffer whose backup pin sits on the always-on rail, or by moving the single-rail buffer into a nearby always-on voltage area. Then legalize and re-check.
  28. 28 Secondary PG constraints conflict or leave dual-rail cells unplaceable. What do you do?Expert: Secondary PG constraints tell the placer where each secondary supply really has straps, and they conflict when user regions, tool-derived regions, the UPF and the netlist disagree. Run `check_secondary_pg_placement_constraints` (ICC2), read which pairs disagree, fix the source rather than relying on commit-time resolution, and re-commit. If dual-rail cells still cannot be placed, the allowed regions are too small for them, so widen the margin, add straps or relax the cell-type filter.
  29. 29 How do you choose the daisy-chain length and order of the switches?Expert: Chain length sets how long the enable takes to ripple through every switch, which sets both wake-up time and peak in-rush: a longer chain means a slower wake and a lower peak. You pick the number of parallel chains so wake-up meets the controller budget while peak current stays under what the grid can supply. Order the chain so it starts near the supply entry and the controller, and ends where the ack returns.
  30. 30 How do you implement a multivoltage design hierarchically in ICC2?Expert: You split the flat design and its UPF into blocks, shape the blocks so their voltage areas fit, build top-level straps, and push a PG strategy down to each block. Each block then builds its own PG and secondary PG constraints and is implemented against its block UPF, while the top commits the block constraints and checks everything together. The order matters because each step uses data the previous one produced.
  31. 31 What are disjoint voltage areas, and how does ICC2 derive them automatically?Expert: A disjoint voltage area is one voltage area made of separate, non-touching shapes, so one power domain can sit in several islands of the floorplan. You use it when the logic of a domain wants to live next to different things, such as two memories or two sets of pads, and one compact shape would stretch the routes to both. ICC2 can derive such shapes with `derive_disjoint_voltage_areas_ml` (ICC2), a machine-learning feature that reads the netlist, UPF and timing constraints, and you should treat its output as a proposal you check for power, switches and routing, not a finished floorplan.
  32. 32 A feedthrough crosses a domain with no voltage area defined yet. What breaks, and how do you handle it?Expert: With a voltage area missing, ICC2 puts that domain in DEFAULT_VA, and it only buffers a feedthrough through the domain if the domain primary supply matches the top domain primary. Everything you implement there is provisional: buffers may sit on a supply that later turns out to be switched, and checks that need the real VA cannot run properly. Keep the net known, assign feedthrough supplies explicitly, and re-check once the voltage area exists.
  33. 33 How does ICC2 legalize always-on buffers that already exist in the RTL netlist?Expert: Buffers and inverters written in the RTL are hard terminals with a fixed supply, so on an always-on net inside a shutdown domain they create violations the tool cannot fix by adding cells around them. AO legalization lets ICC2 change their supply: it converts single-rail ones to dual-rail user library cells, or back, at the same time as level-shifter insertion. You enable it with `mv.upf.ao_legalize_gtech_buf` (ICC2) for GTECH cells, or run `create_mv_cells -always_on` (ICC2) to cover every buffer and inverter.
  34. 34 Why do tie cells cause multivoltage violations, and how do you fix them?Expert: A tie cell drives a constant, but that constant is only valid while the tie cell supply is on and at the right voltage. When you add tie cells by hand, ICC2 uses single-rail ones, which take the domain primary supply; if the load wants a different supply, `check_mv_design` (ICC2) reports a voltage or isolation violation. `fix_mv_design -tie_cell` (ICC2) repairs them by switching between single-rail and dual-rail tie cells or reconnecting the backup PG pin.
  35. 35 After a late ECO, isolation or level shifters are missing. What's your triage flow?Expert: A late ECO can add ports and domain crossings that no isolation or level-shifter strategy was written for, so the cells are never inserted. Triage in a fixed order: find every new crossing with `check_mv_design` (ICC2), fix the power intent first, insert cells with `create_mv_cells` (ICC2), then rerun `check_lp -stage design` (VCLP) as the independent signoff check.
  36. 36 The tools report power-state conflicts. How do you resolve them?Expert: A power-state conflict means two parts of the power intent disagree: connected supplies carry different states, or a parent PST uses a voltage the child never defined, so the merge drops that state. Identify which case you have with `report_pst -reconcile` (ICC2) and `report_system_pst` (VCLP), then fix the UPF at its source instead of loosening checks until the message goes away.
  37. 37 What is the golden UPF flow, and why use it instead of save_upf at every step?Expert: In the golden UPF flow you never rewrite the RTL power intent: every tool reads the original file plus supplemental UPF files that hold only tool-made changes. You enable it with `mv.upf.enable_golden_upf` (ICC2) before loading the UPF and write changes with `save_upf -format supplemental` (ICC2), so reviewers, PT and VC LP all check the same intent.
  38. 38 How do you sign off timing for a DVFS design in PrimeTime?Expert: You can run one scenario per voltage combination, but the count grows as levels to the power of domains and it is easy to skip a mixed pair. Simultaneous multivoltage analysis (SMVA) in PrimeTime times every path under every legal combination of its domains' levels in one run, which catches the cross-domain path that fails only when one side is fast and the other slow.
  39. 39 How do you analyze in-rush current when a domain powers up?Expert: Ramp-up analysis in RedHawk simulates a switched domain turning on: switch models, the domain's capacitance and the real enable timing give the total in-rush current and the virtual-rail voltage over time. Run `perform analysis -lowpower` (RH) after the usual power and extraction steps, then read `virtual_domain_total_i.rpt` (RH) for current and `virtual_domain_worst_v.rpt` (RH) for the ramp.
  40. 40 When a domain wakes up, why can always-on neighbours fail, and how do you check it?Expert: A waking domain draws its in-rush current through the same straps, vias and bumps that feed the always-on logic around it, so neighbours see a dynamic drop exactly while they may be busy. Check it with a RedHawk ramp-up run in mixed mode, where `setup analysis_mode lowpower` (RH) is combined with `perform analysis -dynamic` (RH), and judge the always-on region during the wake window, not just the switched domain.
  41. 41 Scan paths are failing isolation checks across domains. How do you resolve them?Expert: DFT insertion creates new ports and nets that cross power domains, and the functional isolation strategies often do not cover them. Run `check_isolation_coverage -dft_signals` (ICC2) to list the violating scan paths with suggested strategies, then fix them one of two ways: add strategies and rerun `insert_dft` (ICC2), or add incremental `set_dft_isolation` (ICC2) rules and apply them with `commit_dft_isolation` (ICC2).
  42. 42 What are PVT mismatches on multivoltage cells, and how do you fix them?Expert: A PVT mismatch means a cell is linked to a library pane whose process, voltage or temperature does not match the operating condition of the supplies it sits on, such as a level shifter characterized at 1.0 V in and out sitting on a 0.9 V input rail. ICC2 picks power management cells by the rule in `opt.common.pvt_setting` (ICC2); `report_pvt` (ICC2) marks which of P, V or T is off, and `fix_mv_design -verbose` (ICC2) reports PVT violations on buffers, inverters, tie cells and diodes.
  43. 43 How do you choose activity and corners for power signoff?Expert: Match the activity source to the question you are answering: default toggle rates for early budgets, SAIF from realistic use-case simulation for average power, and a VCD window around the worst event for peak power. Then pick the corner that makes that number worst, which is the fast, high-voltage, hot corner for leakage and the highest mode voltage for dynamic power.
  44. 44 Synthesis says 120 mW and signoff says 165 mW. How do you find the gap?Expert: Synthesis power has an ideal clock, estimated wire capacitance and often different activity, so it is expected to read low. Find the gap by running both netlists through the same corner and activity file and comparing `report_power -groups` (PT) group by group, then check clock network, wire capacitance, glitch, annotation and leakage in turn, one cause at a time.
  45. 45 What is successive refinement of the UPF, and how does -update work?Expert: Successive refinement means power intent grows in layers: the IP provider writes constraint UPF, the integrator adds configuration such as strategies and control signals, and implementation adds supplies and cell detail. Each later layer refines earlier commands with **-update** instead of rewriting them, so an IP's constraints travel unchanged into every chip that uses it.
  46. 46 How are nets with loads in several domains, or nets driven by constants, isolated?Expert: When one driver fans out to loads on different supplies, a port-based strategy cannot say which branch needs isolation, so you describe it by supplies: **-source**, **-sink** and **-diff_supply_only** on `set_isolation` (UPF) put cells only on branches whose load supply differs from the driver. Nets driven by literal constants count as real drivers with a related supply, and ICC2 can skip isolation where the constant already equals the clamp value.
  47. 47 When several retention strategies could apply to a register, which one wins?Expert: ICC2 resolves overlapping retention strategies by granularity, not by the order you wrote them: an explicitly named register beats a Verilog process or always block, which beats an instance, which beats a strategy that names only the domain. A -no_retention strategy outranks a retaining one, but a finer retaining strategy still wins over a coarser -no_retention, and a true tie goes to the strategy created first.
  48. 48 After wake-up, retained registers come back with wrong values. How do you debug it?Expert: Wrong values after wake-up almost always come from the control sequence or the retention supply, not the flop. Check in order that the retention supply stayed on, that RESTORE came after the primary rail was stable and before clocks restarted, that save and restore polarity match the cells, and, for zero-pin retention cells, that `check_lp -stage design` (VCLP) reports no RET_CLAMP_INVERT.
  49. 49 Walk through the complete shutdown and wake-up sequence of a switchable domain.Expert: Shutdown runs stop clocks, assert isolation, save state, then switch off and wait for the acknowledge. Wake-up is the mirror: switch on and wait for the acknowledge, restore state, release isolation, then restart clocks, and swapping any two neighbouring steps either corrupts retained state or lets unknown values reach always-on logic.
  50. 50 How is well (body) biasing implemented in ICC2?Expert: Well biasing drives the n-wells and p-wells from dedicated supplies instead of the rails, which shifts transistor threshold voltage: reverse bias cuts leakage and forward bias buys speed. In ICC2 you turn on the UPF-based bias mode with the enable_bias design attribute, supply sets in bias scopes then gain nwell and pwell functions that connect implicitly to bias PG pins, and `check_mv_design` (ICC2) enforces the bias rules.

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