Low-Power VLSI & UPF Physical Design Mentor Guide, 160 questions
Master low-power physical design and UPF intent through 160 complete answers covering power domains, multivoltage rules, isolation, level shifters, and signoff.
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Dynamic power flows only when nodes switch: every 0-to-1 transition charges a capacitance from the supply. Leakage power flows all the time the transistors are powered, even with the clock stopped, because off transistors are never fully off. You cut dynamic power by switching less or at lower voltage, and leakage by using higher-Vt cells or removing the supply.
The three components are switching power, short-circuit power, and glitch power. Switching power charges the load capacitance on every useful transition, short-circuit power flows while both transistors conduct during a slow input edge, and glitch power comes from extra, unwanted transitions before a node settles. In libraries, the short-circuit part is usually modelled inside the cell as internal power.
An off transistor still conducts a small current through three main paths: subthreshold conduction under the channel, tunnelling through the gate oxide, and reverse-biased junction leakage including GIDL. At advanced nodes subthreshold leakage dominates, because threshold voltages were lowered to keep gates fast. Gate leakage was brought down by high-k metal gates, so it matters less than it once did.
LVT cells switch faster because they turn on at a lower gate voltage, but they leak much more when off. HVT cells leak far less but are slower. You use HVT everywhere timing allows and spend LVT only on paths that cannot meet timing otherwise.
Leakage rises steeply with temperature, because heat lowers the threshold voltage and increases subthreshold and junction current. Illustratively, a block can leak several times more at 125 °C than at 25 °C. That creates a feedback loop: more leakage makes more heat, which makes more leakage.
A fast (FF) corner has lower thresholds and stronger transistors, so it has the worst leakage and runs fastest. A slow (SS) corner has the least leakage but the worst setup timing. So the corner that fails timing is rarely the corner that fails power, and you sign off each at its own worst case.
For leakage, the worst case is fast process, maximum voltage and maximum junction temperature, because every one of those raises off-current. For dynamic and peak power, the worst case is maximum voltage with the activity of the busiest real mode. Average battery power is usually reported separately at typical conditions with realistic use-case activity.
Dynamic power scales with the square of supply voltage, so a small voltage cut gives a large power saving, and leakage drops too. The price is speed: gate delay rises as Vdd gets closer to the threshold voltage. Below a floor set by Vt and memory stability, the logic slows badly or stops working reliably.
A power domain is a group of instances that are treated as one unit for power management, and that normally share one primary supply. Everything in it powers up, powers down or changes voltage together. The domain is also where you attach the strategies for its boundary: isolation, level shifting and retention.
A phone SoC is the classic example: the big CPU cluster, the GPU and the modem each sit in their own switchable domain, and a small always-on domain keeps the power controller, real-time clock and wake-up logic alive. Each switchable domain turns off or scales its voltage based on what the phone is doing. The always-on domain decides when they come back.
A domain can be fixed (one voltage, always on), switchable (power can be cut), DVS (voltage changes at run time), DFS (clock frequency changes) or DVFS (voltage and frequency change together). Each type adds its own hardware and verification. The more a domain can change, the more crossings and states you have to check.
A supply port is the entry point where power crosses a boundary, such as a chip pad or a block pin. A supply net is the wire that carries that power inside a scope, and connecting a net to a port joins them. UPF builds the power network from these two objects before any domain can use a supply.
A supply set is a named bundle of supply functions, power and ground, plus optional bias functions, that together form one complete power source. Instead of naming each net, you hand a domain or strategy the bundle. You can refer to its functions, such as SS_COP.power, and bind them to real nets now or later.
The primary power and ground of a domain are the default supply for every cell in it: any instance without an explicit supply connection gets them automatically. In IEEE 1801-2015 you give them as the domain's primary supply set; older UPF named the nets directly. Physically, they are the rails that the standard-cell rows in that domain sit on.
Primary power runs the whole domain and is the supply that turns off when the domain shuts down. Backup, or retention, power is a separate always-on supply that keeps a small part of each retention flop alive, so the saved bit survives. In Liberty the two show up as different pin roles on the same cell: primary_power and backup_power.
A switched supply sits behind a power switch and disappears when the switch opens; it is often called the virtual rail. An always-on supply comes straight from the regulator and never turns off during operation. The switch, its control path, isolation cells and retention latches must run on the always-on supply, because they have to work while the switched rail is off.
Power-down means the power controller opens the switch in front of a domain so its rail decays to 0 V and the logic inside stops leaking. Power-up means closing the switch again, letting the rail ramp back to full voltage, and bringing the logic back to a known state before it is used. Both are ordered sequences run by always-on logic, not a single flip of a switch.
A power state table (PST) lists the combinations of supply values the chip is allowed to be in at the same time. Each row is one legal mode, such as all domains on, or the GPU off while the CPU runs at low voltage. Implementation and checking tools use it to decide which crossings need level shifters and isolation.
A valid signal sits at a clean logic 0 or logic 1, driven by a powered gate. When a domain shuts down, its outputs are no longer driven, so they float or settle somewhere between the rails. That invalid value can waste power in the receiving gate and make always-on logic act on garbage.
An isolation cell is a small gate on a signal leaving a domain that can switch off, and it forces that signal to a known value while the domain is off. It exists because an unpowered driver leaves the net floating, and the always-on receiver would otherwise read garbage and leak current. The cell is powered from a supply that stays on and is controlled by an enable from always-on logic.
An AND-type isolation cell clamps its output to 0, and an OR-type isolation cell clamps its output to 1. The AND gate clamps when its enable input goes low, and the OR gate clamps when its enable goes high. In UPF you choose between them with the clamp value of the isolation strategy, and the tool maps that to the right cell.
A level shifter is a cell that converts a signal from the voltage swing of one domain to the swing of another. It is needed because a logic 1 from a lower-voltage domain is not high enough to turn off the PMOS of a gate on a higher supply. Without it the receiver leaks crowbar current and may switch late or read the wrong value.
A low-to-high crossing goes from a lower-voltage domain into a higher one, and a high-to-low crossing goes the other way. Low-to-high needs a level shifter, because the weak input cannot turn off the receiver PMOS. High-to-low often works without one, so it depends on the library and the threshold you set.
An enable level shifter is one cell that does both jobs at a boundary: it shifts the voltage while the source is on and clamps the output while the source is off. You use it where a signal leaves a switchable domain and also changes voltage. It saves area and delay compared with a separate isolation cell plus level shifter.
A power switch is a large transistor cell placed between a real supply rail and a domain, so the power controller can disconnect that domain. When it is off, the domain's rail collapses and both dynamic and leakage power in the domain drop to near zero. You pay for it with area, a small IR drop through the switch, and wake-up time.
A header switch is a PMOS transistor between the real power rail VDD and the domain's virtual power rail. A footer switch is an NMOS transistor between the domain's virtual ground and the real ground VSS. Both cut the same current path, just from different sides.
A mother-daughter configuration pairs a weak switch transistor with a strong one on the same rail. The weak one turns on first and charges the domain slowly, and the strong one turns on after to give full current with low resistance. Staging this way keeps the in-rush current peak small, so neighbours on the same supply do not see a voltage dip.
A virtual rail is the supply net on the output side of a power switch, and it only exists behind that switch. The real supply feeds the switch and is always driven, while the virtual rail goes to 0 V whenever the switch is off. For a switchable domain, the virtual rail is the domain's primary supply.
A switched ground net is the ground rail of a domain that reaches real ground only through a footer switch. The footer is an NMOS transistor between that net, often called VVSS, and the real VSS. When the footer opens, VVSS is cut off from VSS and drifts up toward VDD, so the domain stops conducting.
The isolation control signal is the enable that tells isolation cells when to clamp. It must stay driven while the protected domain is off, because the clamp has to hold for the entire shutdown. So it comes from always-on logic and is buffered only by always-on cells along its whole route.
Retention signals are the control inputs, usually SAVE and RESTORE, that tell retention registers when to copy their state into a backup latch and when to copy it back. The always-on power controller drives them around each power-down and wake-up. Without them the domain loses its state and must fully reset and reinitialise on every wake-up, which costs time, energy and a software setup pass.
Save means copying the main flop's value into a small shadow latch that stays powered. Restore means copying that value back into the main flop after power returns. Between the two, the main flop is off and only the shadow latch holds the state.
An always-on cell is a buffer, inverter or similar cell that keeps working while the domain around it is off, because it has a backup supply pin tied to an always-on rail. It is placed inside the shutdown voltage area, on nets that must stay alive there. Its secondary power pin is routed to a nearby always-on strap.
Power intent is the description of how a chip is powered: which logic sits on which supply, which blocks can switch off, and what each domain boundary needs to stay safe. It lives in a separate UPF (IEEE 1801) file because RTL describes function, not supplies, and one file read by synthesis, P&R, timing and simulation keeps every tool working from the same power plan.
`create_power_domain` (UPF) names a power domain and lists the instances that belong to it, so every cell in those instances shares one primary supply and one set of strategies. The domain is created in the current scope, and every instance in the design must end up in exactly one domain.
Multivoltage design runs different blocks of one die at different supply voltages. Blocks that need speed get a higher voltage, and everything else runs lower to save power, since dynamic power scales with the square of the voltage.
A voltage crossing is a net whose driver and receiver sit in power domains at different voltages. Every domain crossing raises two questions: does the signal need a level shifter, and does it need isolation because the driver can be off while the receiver is on?
`check_mv_design` (ICC2) checks the netlist against the UPF and reports electrical mistakes. By default it looks for missing level shifters and isolation cells, strategies that disagree with the power state table, and supply and PG-pin rule problems. PG-net and PG-connection checks, such as supply nets without a voltage, run only when you add `-pg_netlist` or `-all`.
A missing isolation cell leaves an output of a switchable domain driving always-on logic with nothing to hold it when the source powers down. The receiver sees a floating value, which causes crowbar current and random logic behaviour only when the domain actually turns off.
Adiabatic logic charges each load slowly from a ramping supply, called a power clock, instead of a fixed step. If the ramp is much slower than the RC time constant, most of the energy is returned to the supply rather than burned as heat. It is rare in standard-cell ASIC flows because it needs special cells, multi-phase power clocks and low speed.
Battery-aware design judges a chip by the shape of its current draw, not just its average power. Peukert's law says a battery delivers less total charge when drained at a higher current, so a bursty design can run out sooner than a smooth one with the same average.
DVFS (dynamic voltage and frequency scaling) changes a domain's supply voltage and clock frequency at run time to match the workload. The safe rule is: raise voltage before frequency when going up, and lower frequency before voltage when going down, so the logic is never clocked faster than its current voltage supports.
Bus-invert encoding sends either the data word or its complement, whichever flips fewer wires compared with the value already on the bus. One extra flag wire tells the receiver which version it got, capping toggles at about half the bus width per transfer. The saving is largest on long, busy buses carrying random data.
In Gray code, consecutive values differ in exactly one bit, while a binary increment can flip many bits at once. For counters and address buses that step sequentially, that keeps toggles to one per step and cuts switching power, as long as the value really does move by one each time.
The stack effect is the drop in subthreshold leakage when two or more off transistors sit in series. The node between them rises to a small positive voltage, which pushes the upper transistor harder off and cuts the voltage across the lower one, so the stack leaks much less than a single off transistor.
Operand isolation holds the inputs of a combinational block, such as a multiplier, at a constant when its result is not needed, so its internal logic stops switching. Clock gating stops the clock to registers instead. The two are complementary: one saves datapath power, the other saves clock and register power.
A power domain is a logical group of instances in the UPF that share a primary supply. A voltage area is the physical region in the floorplan where those cells may be placed. Usually one domain maps to one voltage area, but several domains with the same primary supply can share one.
A secondary power pin is a second supply pin on a dual-rail cell, fed from a strap other than the row rail it sits on. Always-on buffers, isolation cells, level shifters, retention flops and always-on tie cells use one because they must see a supply the row does not provide.
Switching activity is how often each net toggles and how long it sits at 1. Dynamic power depends directly on it, so the power number is only as good as the activity you feed in: SAIF gives toggle counts, VCD gives full waveforms, and without either the tool falls back to default activity.
Level 2: Construction & Debugging
`create_power_domain` (UPF) names a group of instances that share one primary supply and one set of isolation, level-shifter and retention strategies. It is bookkeeping for the tools, not a netlist cell: nothing gets inserted until strategies act on it. In MYCHIP you create the always-on top domain, then one child domain per block, and confirm the result with `report_power_domains` (ICC2).
You create the entry points with `create_supply_port` (UPF), the wires with `create_supply_net` (UPF), and join them with `connect_supply_net` (UPF). A net created for one domain can be extended into another with `-reuse`, so one physical rail spans the hierarchy. In IEEE 1801-2015 you then bundle nets into supply sets instead of naming them as domain primaries directly.
A supply net is one wire carrying one function, such as VDD1p0 or GND. A supply set is a named bundle of functions (power, ground, and optionally nwell and pwell) that you bind to real nets, so a strategy can say "power this from SS_AON" without listing nets. IEEE 1801-2015 builds domain primaries, isolation supplies and retention supplies on supply sets, created with `create_supply_set` (UPF).
`set_domain_supply_net` (UPF) names the primary power and ground nets of a domain, and every cell in that domain is then implicitly tied to them. IEEE 1801-2015 lists it as legacy: the modern form binds a supply set with `create_power_domain PD_COP -supply {primary SS_COP}` (UPF). Both still load in ICC2 and PrimeTime, so you need to read the old form and write the new one.
`set_isolation` (UPF) tells the tool which boundary ports of a switchable domain need an isolation cell, what powers that cell, and what value it holds while the domain is off. Pair it with a control signal, and the always-on side never sees a floating input.
For `set_isolation` (UPF), IEEE 1801-2015 lists four locations: self (the default), parent, other and fanout; automatic is a `set_level_shifter` (UPF) value in ICC2, not an isolation one. The location decides which domain hosts the cell, and therefore which rail its row gives it. Choose the site where the isolation supply is already on, so you avoid a dual-rail cell and a secondary strap inside a switched area.
The clamp value is what the isolation cell drives while its source domain is off: 0 (an AND-type cell, the ICC2 default), 1 (an OR-type cell) or latch (holds the last value). Choose it signal by signal, from what the always-on receiver treats as inactive, not one value per domain. Active-high enables clamp to 0, active-low resets clamp to 1, and buses that must keep their last value use latch.
`set_level_shifter` (UPF) tells the tool which ports of a domain get level shifters, for which voltage direction, and in which domain the cell sits. Low-to-high crossings always need a shifter; high-to-low ones depend on the library and the voltage gap, which is what `-rule` and `-threshold` let you filter. Without any strategy, ICC2 still inserts shifters from the voltages in the power states.
Pick the side where the shifter can get both supplies cheaply: its row rail gives one supply and a secondary pin must reach the other. Self puts the cell inside the domain whose port is shifted; parent puts it in the surrounding domain. For MYCHIP, up-shifters on PD_CPU outputs usually sit in the parent, and down-shifters on PD_CPU inputs sit in self.
`set_retention` (UPF) names which registers in a shutdown domain must keep their state, which supply keeps that state alive, and which signals save and restore it. The register needs two supplies: the switched primary for normal operation and a retention supply that stays on while the primary is off. In IEEE 1801-2015 you give that supply as a set with `-retention_supply` and put the save and restore signals on the same command.
You name each control net and its active level or edge: `-save_signal {U_PC/SAVE high}` and `-restore_signal {U_PC/NRESTORE low}`. In IEEE 1801-2015 these options sit on `set_retention` (UPF) itself; `set_retention_control` (UPF) is the UPF 1.0 form that ICC2 and PrimeTime still accept. The sense you write must match the retention cell pins, or the flop saves and restores at the wrong moments.
`create_power_switch` (UPF) declares an abstract switch that passes an always-on input supply to a switched output supply under a control signal. You name its ports and the nets they connect to, then write Boolean on and off states in terms of the control port. It is one abstract switch in the UPF, later mapped to library cells and built as an array of many cells.
`map_power_switch` (UPF) tells the tools which library cell implements an abstract switch from `create_power_switch` (UPF). In IEEE 1801-2015 the syntax is the switch name followed by a required `-lib_cells` list and an optional `-port_map`. Mapping picks the cell; ICC2 still has to build and connect the physical array.
No single UPF command creates a virtual rail. You declare a separate supply net, make it the output of a power switch fed by the always-on rail, and bind it as the primary of the shutdown domain. In MYCHIP that net is VDD1p0_SW: the switch PD_COP_SW drives it from VDD1p0, and PD_COP runs on it through the supply set SS_COP.
First give each supply port its named states with `add_port_state` (UPF), then declare the table and its column order with `create_pst` (UPF), then add one row per legal mode with `add_pst_state` (UPF). Any combination you do not list is illegal. All three commands are legacy in IEEE 1801-2015, which recommends `add_power_state` (UPF) instead, but ICC2 and PrimeTime still read them.
Always-on control paths carry the signals that manage a shutdown domain, such as isolation enable, save, restore and switch enable, and they must keep working while that domain is off. When such a path runs through a switched voltage area and needs buffering, it needs always-on buffers: cells with a backup supply pin that stays on. ICC2 inserts and legalizes them itself, but only if the library has always-on buffers and the backup supply can reach them.
A feedthrough path is a net that passes through a domain without being used there, for example a PD_CPU to PD_MYCHIP signal routed across the PD_COP area. If it gets buffered on the switched supply of the area it crosses, the net dies whenever that domain is off, even though both its ends are on. ICC2 handles this with always-on or dual-rail buffers, and the UPF can also mark ports that are shorted inside a block as feedthroughs.
Hierarchy in UPF comes from scope: every command acts in the current scope, and you move it with `set_scope` (UPF) or run a block file in place with `load_upf -scope` (UPF). A domain created in a lower scope whose elements sit inside a parent domain simply nests there. `create_composite_domain` (UPF) groups several domains under one name for shared strategies, but it has no physical region.
The tool only uses a cell for isolation, level shifting, switching, retention or always-on buffering if its Liberty model says so. Each type has a cell flag, such as is_isolation_cell or is_level_shifter, plus pin attributes that mark enable pins, PG pin types and which supply each signal pin belongs to. You check what the tool actually read with `report_mv_lib_cells` (ICC2).
Start with what the tool resolved: `report_power_domains` (ICC2), `report_supply_sets` (ICC2) and `report_pst` (ICC2). Then check what it built with `report_mv_cells` (ICC2) and judge the result with `check_mv_design` (ICC2). Repeat the domain and supply reports in PrimeTime so signoff reads the same intent.
ECRL (Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) are dual-rail adiabatic gate families. Instead of a fixed VDD, each gate hangs off a slowly ramping power-clock, so the output charges gently and most of the charge flows back to the supply when the clock ramps down. They differ in where the logic trees sit and how cleanly the outputs swing, and both need a multi-phase power-clock generator that standard ASIC flows do not provide.
AVS trims a domain's supply voltage in a closed loop, using on-die monitors that measure how fast this particular die is right now. DVFS picks a voltage from a fixed table built for the slowest die at the worst temperature, so it wastes margin on typical and fast silicon. AVS runs on top of DVFS: DVFS chooses the frequency, and AVS finds the lowest voltage that still meets it.
VTCMOS changes transistor threshold voltage at runtime by driving the wells from a body-bias generator instead of tying them to VDD and VSS. In standby it applies reverse body bias to raise Vt and cut subthreshold leakage, and in active mode it returns to zero or forward bias for full speed. The block keeps its state because the supply stays on; only the wells move.
DTCMOS ties each transistor's body to its own gate, so the threshold voltage follows the input. When the gate turns the device on, the body forward-biases and Vt drops for more drive; when the gate is off, the body returns to the source level and Vt stays high for low leakage. There is no bias generator, but the supply must stay below the body diode turn-on voltage, which limits DTCMOS to very low-voltage designs.
Light sleep, deep sleep and shutdown are three increasingly deep memory power modes. Each one saves more leakage than the one before and takes longer to wake, and only shutdown loses the stored data. The right choice depends on how long the memory will stay idle compared with the energy and time it costs to wake it up.
Fine-grain clock gating stops the clock to a small group of registers that share an enable, usually inserted by synthesis from RTL enable logic. Coarse-grain gating stops the clock at a branch or block root, so the buffers under it stop toggling too. Both use an ICG cell, which latches the enable while the clock is low so the gated clock never glitches, something a bare AND gate cannot guarantee.
UPF and CPF are both Tcl-based languages that describe power intent outside the RTL: domains, supplies, isolation, level shifting, retention and power states. UPF started at Accellera and became IEEE 1801, while CPF came from the Si2 consortium with Cadence behind it. The industry settled on UPF because an IEEE standard gave every tool vendor a single target, and Cadence tools now read UPF too, so a UPF file travels across vendors.
`create_voltage_area` (ICC2) turns a UPF power domain into a physical region where that domain's cells must be placed; the placer treats it like an exclusive move bound. A guard band is a hard keepout ring that grows outward from the voltage area edge, where no cell can sit. It keeps cells of neighbouring domains apart so their power rails and straps can be built without shorts.
Where voltage-area shapes overlap, ICC2 uses stacking order: by default the shape defined last sits on top and owns the overlap. To nest one voltage area inside another, you define the outer one first and the inner one second, so the inner shape is on top and the outer area's effective shape becomes a ring. Define them the other way round and the outer shape masks the inner one, which ends up with no placement area at all.
Two power domains can share one voltage area when their primary supplies are equivalent: connected in the UPF, physically connected, or functionally equivalent with the same power states. You declare the sharing with the `shared_voltage_area` design attribute through `set_design_attributes` (UPF), and one of the domains acts as the primary domain. The shared voltage area gets one power switch implementation, and `connect_power_switch` (ICC2) wires it for all domains in the set.
An array spreads switch cells in columns or a grid through the voltage area, so every standard cell is close to a switch and IR drop stays low. A ring places the switches along the voltage-area boundary, which keeps the core rows free but makes the centre the farthest point from any switch. Arrays suit large or high-current domains; rings suit small domains and hard macros that cannot take switch cells inside.
In a daisy chain, the switch enable enters the first switch cell, and each cell passes a buffered copy to the next, so the switches turn on one after another instead of all at once. That spreads the in-rush current that charges the virtual rail over time and keeps the peak within what the grid can deliver. The output of the last cell comes back as the acknowledge, telling the power controller that every switch is on.
Dual-rail cells in a shutdown domain, such as always-on buffers, isolation cells and level shifters, need a nearby strap for their secondary (backup) supply. By default ICC2 assumes that strap exists everywhere in the voltage area, which is rarely true. Secondary PG placement constraints tell the placer where the straps really are, so dual-rail cells land close enough for short, low-IR secondary PG routes.
Buffers placed inside a shutdown voltage area on an always-on net must stay powered when the domain is off. You use dual-rail always-on buffers whose backup power pin connects to an always-on secondary supply, never single-rail buffers on the switched rail. ICC2 does this automatically during optimization, and `fix_mv_design -buffer` (ICC2) and `create_mv_cells -always_on` (ICC2) repair buffers that are on the wrong supply.
Both methods buffer a net that physically crosses another domain's voltage area. Physical feedthrough buffering places dual-rail buffers in the crossed voltage area and assigns them to that power domain without punching ports, so the logic hierarchy is unchanged. Logical feedthrough buffering is used when the domain is created at a scope below the net, so the tool punches ports into that hierarchy and places the buffer inside it.
The placer treats each voltage area as an exclusive move bound: a domain's cells must go inside its voltage area, and every other cell must stay out. Isolation and level shifter cells follow their strategy location, so they collect along voltage-area edges, and dual-rail cells also need to sit near their secondary straps. Most boundary problems come from crowding at those edges, guard bands that eat space, and cells that end up in the wrong area after an ECO.
A clock that enters a domain at a different voltage needs a level shifter like any other signal, but ICC2 does not insert level shifters on clock nets by default. You name the clock nets in `mv.upf.auto_ls_clock_nets` (ICC2) and allow shifting on ideal nets with `mv.upf.allow_ls_on_ideal_networks` (ICC2). Then you keep the shifted branch balanced, watch duty cycle, and make sure clock buffers feeding always-on logic stay on when their domain powers down.
A dual-rail cell has its primary PG pins on the supply of the domain it sits in and its backup pin on the supply the UPF strategy names, such as the isolation supply. `connect_pg_net -automatic` (ICC2) derives those connections from the committed UPF and the library PG pin data, so you do not wire them by hand. You then check them with `check_mv_design -pg_netlist` (ICC2), because the default `check_mv_design` (ICC2) run skips PG net and PG connection checks.
`create_mv_cells` (ICC2) inserts power management cells from the UPF strategies: isolation cells, level shifters and repeaters, and with its own options retention cells and always-on legalization of buffers. It runs after `load_upf` (ICC2) and before placement, and it is optional because synthesis normally inserts these cells, but it gives early feedback on whether the power intent is feasible. The flow then continues with `check_mv_design` (ICC2), placement and optimization, and `save_upf` (ICC2).
`check_mv_design` (ICC2) prints one section per rule group, from power domain and supply rules through strategy rules to cell rules, with each message followed by an MV-080 total for that message ID. Triage from the top: supply and domain problems cascade into everything below, so fix those first, then strategy conflicts, then individual cells. For any cell or path it flags, `report_mv_path` (ICC2) tells you why a cell was inserted, associated or rejected.
`report_mv_path` (ICC2) traces one multivoltage path through a pin, net or cell and shows every MV cell on it with its supply, drivers, sinks, strategy and power domain. For a level shifter or isolation cell that failed to insert or associate, it prints the reason. You reach for it when `check_mv_design` (ICC2) flags a cell or net and you need to know why.
Check functional and DFT crossings separately. For functional paths, run `check_mv_design -isolation` (ICC2), which checks isolation strategies, isolation cells and the isolation of the netlist, then trace anything it flags with `report_mv_path` (ICC2) to see which strategy applies and why a cell is missing or unassociated. Scan stitching adds crossings the RTL UPF never listed, so after scan insertion run `check_isolation_coverage -dft_signals` (ICC2), which reports DFT paths with an isolation violation that no strategy covers.
Use the early data check manager: `set_early_data_check_policy` (ICC2) sets how each multivoltage check reacts (error, tolerate or repair), and `report_early_data_checks` (ICC2) lists what was relaxed and how often it fired. The older route is the incomplete UPF flow, enabled with `mv.incomplete_upf.enable` (ICC2). Either way the tool is guessing at missing intent, so every relaxed check must be closed before signoff.
PrimeTime reads the UPF with `load_upf` (PT), builds a virtual model of the power network and pushes each supply net voltage down to the PG pins of every leaf cell. You give the voltages with `set_voltage` (PT), and each cell is then timed at its own supply voltage. PT does not read the power state table directly, so your voltages must match the one PST state you mean to verify.
A level shifter is a real cell on the path, and its delay depends on both its input and output supply voltages. PT times it from two-rail libraries characterized at voltage pairs, and separately checks signal levels with `check_timing -include signal_level` (PT) to catch crossings that need a shifter but lack one. `set_level_shifter_threshold` (PT) sets how large a driver-load voltage difference counts as a mismatch.
The isolation enable decides the moment the always-on side stops trusting a domain, so it is a timed event, not a static setting. It must reach every isolation cell and settle before the switched rail starts to fall, and it may only release once the rail is back, the domain is restored and its outputs are valid. The whole path that carries it must stay powered while the domain is off.
A low-power static checker such as VC LP reads the design and the UPF and proves, without simulation, that the power intent is consistent and that the netlist implements it. You run `check_lp` (VCLP) by stage: `-stage upf` for the power intent, `-stage design` for the netlist, and `-stage pg` once the netlist carries power and ground pins. You then read `report_violations -app LP` (VCLP) and waive only what you can justify.
Power-aware simulation runs your RTL or netlist together with the UPF, so supplies can switch off during a test. When a supply set enters a state whose simstate is CORRUPT, the simulator corrupts what it powers: state elements and the nets they drive go to X, and those processes stop evaluating. That turns a missing clamp, a controller that switches in the wrong order, or a retention register restored too early into visible X on signals your testbench already checks.
Scan stitching adds paths the functional UPF never saw: a chain that runs from PD_COP into PD_MYCHIP crosses a domain boundary and needs isolation and level shifting like any data signal. ICC2 covers these with `set_dft_isolation` (ICC2), which reuses an existing isolation strategy for DFT connections, or with a placeholder strategy that `generate_mv_constraints -dft_isolation` (ICC2) fills after `insert_dft` (ICC2). `check_isolation_coverage -dft_signals` (ICC2) then shows what is still uncovered.
Enable PrimePower with `set_app_var power_enable_analysis true` (PT), load the routed netlist with parasitics, constraints and the UPF, read switching activity with `read_saif` (PT) or `read_vcd` (PT), then run `update_power` (PT) and `report_power` (PT). The number is only as good as the activity behind it, so use a simulation of a real use case, not assumed toggle rates. Report by group to see where the power goes.
Glitch power is the energy burned by spurious transitions: when the inputs of a gate arrive at different times, its output can toggle several times before it settles. Each extra toggle charges and discharges real capacitance, so it costs as much as a useful one, and in deep arithmetic logic those wasted edges add up to a real share of the block power. You reduce it by balancing path delays, cutting logic depth with pipelining, and stopping datapaths from toggling when their result is not needed.
Average power sets battery life and steady temperature, but peak power sets what the package, the power grid and the regulator must survive in a single instant. A chip can meet its average budget and still fail when many blocks switch together or a domain wakes up and draws rush current. You plan and check both, because they break different things: average power drains the battery and heats the package, while a peak collapses the supply for a few nanoseconds and fails timing inside that window.
A supply set handle is a named slot on a UPF object, such as a power domain or a strategy, that stands for the supply set used there. ICC2 gives every domain primary, default_isolation and default_retention handles, and `associate_supply_set` (UPF) binds a real supply set such as SS_AON to a handle so both resolve to the same nets. Writing strategies against handles keeps the intent readable and lets you rebind a supply without rewriting every strategy.
IEEE 1801-2015 Annex D marks the PST commands `create_pst` (UPF), `add_pst_state` (UPF) and `add_port_state` (UPF), plus `set_domain_supply_net` (UPF) and the net-based isolation and retention supply options, as legacy, and names a replacement for each. The PST gives way to `add_power_state` (UPF), which defines states on supply sets and domains instead of in one flat table. Tools still accept both forms, and interviews ask about both.
Use `set_port_attributes` (UPF) with `-driver_supply` on inputs and `-receiver_supply` on outputs to say which supply set drives or reads a top-level port; `set_related_supply_net` (UPF) does the same job with supply nets. The tools compare that supply with the domain on the inside to decide whether isolation or a level shifter is needed. Get it wrong and you get missing cells on real crossings, or extra cells on crossings that do not exist.
Use `use_interface_cell` (UPF) to tie an isolation strategy, a level-shifter strategy, or one of each to the library cells you list. It is the only mapping command that can map a combined cell such as an enable level shifter, and in ICC2 it wins over `map_isolation_cell` (UPF) and `map_level_shifter_cell` (UPF) on the same strategy. Then check with `report_mv_lib_cells` (ICC2) that the forced cell really has the attributes the strategy needs.
A single-rail isolation cell has one power pin and runs from the rail of the domain it sits in, so it must sit where that rail stays on during shutdown. A dual-rail cell adds a backup power pin fed by an always-on supply, which lets it sit inside the domain that switches off and keep clamping. ICC2 picks between them from the cell rail information and the location of the strategy, and warns when the choice looks wrong.
They differ in how many retention control pins they have. A two-pin register has separate SAVE and RESTORE pins, a single-pin register uses one save_restore pin whose level selects the mode, and a zero-pin register has no control pin because its subordinate latch sits on an always-on supply. Zero-pin registers only retain if the clock and asynchronous pins are held inactive, so ICC2 inserts clamp cells that you must check.
Run a voltage-drop analysis with RedHawk Fusion, give each switch cell its on-resistance with `set_power_switch_resistance` (ICC2), then run `size_power_switches -max_irdrop` (ICC2) with your drop target. The tool swaps switches for same-footprint cells of a different Vt to meet the target, and skips any switch it cannot improve. You trade drop against switch leakage and area, so check both after the swap.
You close timing with a low-Vt-heavy mix, then swap cells on paths with spare slack to higher-Vt versions of the same footprint, which leak far less. The implementation tool does this during optimization, and PT does it again at signoff with `fix_eco_power` (PT), which backs out any change that creates a timing or DRC violation. You keep a slack guard band, so later crosstalk and variation do not eat the paths you just slowed.
Level 4: Signoff Reasoning
MYCHIP has four power domains: the always-on top PD_MYCHIP on VDD1p0 (1.0 V), an always-on PD_CPU on VDD0p9 (0.9 V), a switchable PD_COP on VDD1p0_SW with retention, and PD_DSP on an external rail VDDdsp that moves between 1.1 V and 0.9 V. The power controller U_PC sits in PD_MYCHIP, drives PSE, ISE and SRE, and reads PSE_ACK back from the PD_COP switch. Every crossing then needs its own strategy: a level shifter where voltages differ, isolation where the driver can be off while the receiver is on.
Each block carries its own UPF, and the top UPF loads it into the block instance with `load_upf -scope` (UPF), then drives the block supply ports from top nets. Top-down, ICC2 cuts the chip intent into block UPFs with `split_constraints` (ICC2); bottom-up, finished blocks come back as ETMs or macros whose port supplies you describe from outside. `create_composite_domain -subdomains` (UPF) only groups existing domains into one container, and a strategy written on it applies to each subdomain; tool support varies by release.
Scope is the instance where you create a domain, and extent is the set of instances that belong to it. One instance can be the scope of several domains but sits in the extent of only one. `-applies_to_boundary` (UPF) on an isolation or level-shifter strategy picks which edge it covers: the upper boundary facing the parent, the lower boundary facing a nested child domain, or both.
A top-level UPF runs in a fixed order: domains, then supply ports and nets, then each domain primary supply, then switches and strategies, and last the power states. In MYCHIP that means four `create_power_domain` (UPF) calls, VDD1p0, VDD0p9, VDDdsp and VSS shared into subdomains with `-reuse`, a switch that makes VDD1p0_SW for PD_COP, and a table of legal rail combinations. Each section may only refer to objects an earlier section created.
Supply sets are related when they resolve to the same nets, which you declare with `associate_supply_set` (UPF). `-resolve` on `create_supply_net` (UPF) decides the state and voltage of a net that has more than one supply source. The default, unresolved, allows one source only, so a net fed by two switches needs one_hot, parallel, parallel_one_hot or a named resolution function.
Modern UPF marks a named state illegal with `-illegal` in `add_power_state` (UPF), and `-complete` declares that any state not defined is illegal too. Legacy PST flows declare illegal combinations by omission: any combination missing from the `add_pst_state` (UPF) rows is not allowed. Implementation reads the legal set to decide where isolation and level shifters go, so a wrong illegal state quietly removes protection.
The controller drives the switch control input, and the switch chain returns an acknowledge once its last cell has turned on. The ack tells the controller the virtual rail is really up, so restore and isolation release happen only after it arrives. In UPF you declare the pair with `-control_port` and `-ack_port` on `create_power_switch` (UPF).
A header is a PMOS switch between the real VDD and the block virtual VDD; a footer is an NMOS switch between the block virtual VSS and the real VSS. Footers are smaller for the same on-resistance because NMOS carries more current per width, but headers keep one shared ground, which multi-voltage designs depend on. Most SoCs pick headers, and the library declares either kind with `define_power_switch_cell` (UPF).
Inside PD_COP the cells run on VDD1p0_SW, a virtual rail that exists only while the header switches conduct, while VDD1p0 outside stays flat at 1.0 V. When the switches open, VDD1p0_SW decays slowly as leakage drains it and internal nodes float, and even when on it sits below VDD1p0 by the switch IR drop. Isolation, retention and always-on cells in PD_COP must therefore tap VDD1p0, never the virtual rail.
A retention flop keeps its normal-mode logic on the switched primary, VDD1p0_SW, and its shadow latch on an always-on retention supply, VDD1p0. You name that supply with `-retention_supply` on `set_retention` (UPF), or with the legacy net options. `-use_retention_as_primary` (UPF) goes further: the register and its output run from the retention supply, which changes the driver supply that isolation and level-shifter strategies see.
When two isolation strategies could claim the same port, ICC2 ranks them in a fixed seven-level order, highest first: ports named in `-elements`, ports implied by an instance in `-elements`, ports implied by the domain name alone, `-no_isolation`, `-source` with `-sink` (both beats one), `-diff_supply_only` true, and `-diff_supply_only` false. The order of execution does not matter. If two strategies still conflict, the one created first keeps the port and later ones lose it.
The ICC2 MV UG documents automatic, self, parent and other as `-location` values for `set_level_shifter` (UPF), and IEEE 1801-2015 also lists fanout; there is no sibling value in either. `-rule` and `-threshold` decide which crossings a strategy covers, and when strategies overlap ICC2 ranks `-elements` (port over instance over domain) first, then `-no_shift`, then `-source` or `-sink`, then the rest. Choose the location where both supplies are available and the fanout stays cheap.
Always-on logic is whatever must keep working inside a shutdown domain: retention cells, isolation cells, and the save, restore and isolation-enable paths that reach them. ICC2 builds it automatically, but only if the target library has always-on buffers and inverters marked with the `always_on` attribute. It then marks as always-on logic any buffer, inverter or tie cell whose supply differs from the primary supply of the domain it sits in.
When ICC2 punches new hierarchical ports for retention, switch or isolation control nets, it derives a `-no_isolation` strategy on them so existing strategies do not grab them. If the control driver can be off while the port receiver is on, that becomes an isolation violation you cannot fix with your own strategies. Setting `mv.cells.smart_derive_iso_strategy_on_new_control_ports` (ICC2) to true makes the tool check the PST first and derive `-no_isolation` only where there is no violation.
`analyze_mv_feasibility` (ICC2) is a static low-power check that asks whether every isolation, enable-level-shifter, retention and level-shifter strategy can be mapped to a real library cell. If one cannot, it issues UPF-909, returns a Tcl status of 0, and lists each failing element with the check that failed, such as a data inversion or PVT mismatch. Run it after `load_upf` (ICC2) and before implementation, and add `-level_shifter -format html` for the detailed shifter report.
The clamp value is what the always-on receiver sees while the source domain is off, so it must be the inactive level of that signal: 0 for an active-high enable, 1 for an active-low reset. Get it wrong and the receiver acts on a fake event as soon as isolation turns on, such as starting a DMA or resetting a block. Power-aware simulation shows it as a spurious event at shutdown, and static checks catch it only when the intended clamp is written down with `set_port_attributes -clamp_value` (UPF).
If `-retention_supply` (UPF) points at a switched supply such as VDD1p0_SW, the shadow latches die with the domain and every retained value is lost at shutdown. Nothing fails until wake-up, when restore loads garbage. UPF helps in two ways: in implementation a missing retention supply is an error, and in simulation the default RET_SUP_COR semantics corrupt the register whenever its retention supply is off, so the bug shows up as X.
If the sense you declare in `-save_signal` or `-restore_signal` (UPF) does not match how the power controller drives the pin, the retention flop saves at the wrong edge or restores at the wrong time, and the domain wakes up with stale or corrupt state. No option inside `set_retention` (UPF) checks polarity during implementation. You catch it with a mutex checker attached by `bind_checker` (UPF) in power-aware simulation, backed by VC LP static checks.
UPF talks about supply sets and strategies, while the library describes real PG pins, pin types and related-power attributes; a mismatch means the tool cannot connect one to the other. There is no single reconcile command: the Liberty PG attributes decide most of it, and for macro and top-level ports you override them with `set_port_attributes -receiver_supply` (UPF), its `-driver_supply` twin, or `set_related_supply_net` (UPF). `report_mv_lib_cells` and `check_mv_design` (ICC2) show where the two views disagree.
You load the UPF, insert and check the power-management cells, build voltage areas, switches and secondary PG, then place, clock and route with the MV rules on, and re-run `check_mv_design` (ICC2) after every step. Signoff closes timing in PrimeTime against the same UPF and checks wake-up current and IR drop in RedHawk. The Early Data Check Manager decides which data problems stop the flow and which the tool tolerates or repairs.
Every independent supply multiplies the number of possible system states, so N supplies with k states each give k to the power N combinations. Tools, verification and your own review all scale with that number, which is why real designs declare only the handful of states the product uses and mark the rest illegal. It also pushes architects to tie domains together so they switch as a group instead of independently.
Size the switch bank so its combined on-resistance, times the peak current of the domain, stays inside the IR-drop budget of the virtual rail. That sets a minimum switch count; the upper limit comes from area, the switches own off-state leakage and wake-up rush current. Undersize it and every path in the domain runs slow; oversize it and you pay leakage, area and a larger in-rush spike.
DVTS changes the supply voltage and the transistor threshold together at run time: VDD through the regulator, Vt through body bias on the wells. At a low-performance point it lowers VDD and applies reverse bias to raise Vt and cut leakage; at a high-performance point it raises VDD and applies forward bias to lower Vt for extra speed. DVFS alone moves only one of those two levers, so at low speed it still pays the full leakage of a fixed, fast Vt.
When a switched domain wakes, its whole capacitance charges from 0 V through the switches, and if they all turn on at once the charging current spikes far above normal load. That spike pulls down the shared always-on supply and can upset neighbours, including the controller doing the wake-up. Daisy-chaining the switch enables spreads the turn-on over time, trading a longer wake-up for a much lower peak.
Put the voltage area close to its supply bumps, spread the switches evenly under the always-on straps so every region of the block has a short path to one, and reserve an always-on channel for the cells that must stay alive. Then check static and dynamic IR on both the real and switched rails, and ramp-up current for the chosen enable order. Switch count sets IR drop; switch enable order sets wake-up time and in-rush.
The strategy `-location` decides which domain a cell belongs to, and the domain decides which voltage area it may be placed in, so a cell in the wrong VA is almost always a location or domain problem, not a placer bug. Start from `check_mv_design` (ICC2), then trace the cell with `report_mv_path -cell` (ICC2) to see its strategy, supplies and domain. Fix the strategy or make the missing supply available, then re-insert rather than hand-moving the cell.
Power-aware simulation shows an always-on signal going to X when the domain shuts down, and `check_mv_design` (ICC2) reports an isolation violation on its buffer tree, because the buffer supply is less always-on than its loads. `fix_mv_design -buffer` (ICC2) repairs it, either by swapping to a dual-rail buffer whose backup pin sits on the always-on rail, or by moving the single-rail buffer into a nearby always-on voltage area. Then legalize and re-check.
Secondary PG constraints tell the placer where each secondary supply really has straps, and they conflict when user regions, tool-derived regions, the UPF and the netlist disagree. Run `check_secondary_pg_placement_constraints` (ICC2), read which pairs disagree, fix the source rather than relying on commit-time resolution, and re-commit. If dual-rail cells still cannot be placed, the allowed regions are too small for them, so widen the margin, add straps or relax the cell-type filter.
Chain length sets how long the enable takes to ripple through every switch, which sets both wake-up time and peak in-rush: a longer chain means a slower wake and a lower peak. You pick the number of parallel chains so wake-up meets the controller budget while peak current stays under what the grid can supply. Order the chain so it starts near the supply entry and the controller, and ends where the ack returns.
You split the flat design and its UPF into blocks, shape the blocks so their voltage areas fit, build top-level straps, and push a PG strategy down to each block. Each block then builds its own PG and secondary PG constraints and is implemented against its block UPF, while the top commits the block constraints and checks everything together. The order matters because each step uses data the previous one produced.
A disjoint voltage area is one voltage area made of separate, non-touching shapes, so one power domain can sit in several islands of the floorplan. You use it when the logic of a domain wants to live next to different things, such as two memories or two sets of pads, and one compact shape would stretch the routes to both. ICC2 can derive such shapes with `derive_disjoint_voltage_areas_ml` (ICC2), a machine-learning feature that reads the netlist, UPF and timing constraints, and you should treat its output as a proposal you check for power, switches and routing, not a finished floorplan.
With a voltage area missing, ICC2 puts that domain in DEFAULT_VA, and it only buffers a feedthrough through the domain if the domain primary supply matches the top domain primary. Everything you implement there is provisional: buffers may sit on a supply that later turns out to be switched, and checks that need the real VA cannot run properly. Keep the net known, assign feedthrough supplies explicitly, and re-check once the voltage area exists.
Buffers and inverters written in the RTL are hard terminals with a fixed supply, so on an always-on net inside a shutdown domain they create violations the tool cannot fix by adding cells around them. AO legalization lets ICC2 change their supply: it converts single-rail ones to dual-rail user library cells, or back, at the same time as level-shifter insertion. You enable it with `mv.upf.ao_legalize_gtech_buf` (ICC2) for GTECH cells, or run `create_mv_cells -always_on` (ICC2) to cover every buffer and inverter.
A tie cell drives a constant, but that constant is only valid while the tie cell supply is on and at the right voltage. When you add tie cells by hand, ICC2 uses single-rail ones, which take the domain primary supply; if the load wants a different supply, `check_mv_design` (ICC2) reports a voltage or isolation violation. `fix_mv_design -tie_cell` (ICC2) repairs them by switching between single-rail and dual-rail tie cells or reconnecting the backup PG pin.
A late ECO can add ports and domain crossings that no isolation or level-shifter strategy was written for, so the cells are never inserted. Triage in a fixed order: find every new crossing with `check_mv_design` (ICC2), fix the power intent first, insert cells with `create_mv_cells` (ICC2), then rerun `check_lp -stage design` (VCLP) as the independent signoff check.
A power-state conflict means two parts of the power intent disagree: connected supplies carry different states, or a parent PST uses a voltage the child never defined, so the merge drops that state. Identify which case you have with `report_pst -reconcile` (ICC2) and `report_system_pst` (VCLP), then fix the UPF at its source instead of loosening checks until the message goes away.
In the golden UPF flow you never rewrite the RTL power intent: every tool reads the original file plus supplemental UPF files that hold only tool-made changes. You enable it with `mv.upf.enable_golden_upf` (ICC2) before loading the UPF and write changes with `save_upf -format supplemental` (ICC2), so reviewers, PT and VC LP all check the same intent.
You can run one scenario per voltage combination, but the count grows as levels to the power of domains and it is easy to skip a mixed pair. Simultaneous multivoltage analysis (SMVA) in PrimeTime times every path under every legal combination of its domains' levels in one run, which catches the cross-domain path that fails only when one side is fast and the other slow.
Ramp-up analysis in RedHawk simulates a switched domain turning on: switch models, the domain's capacitance and the real enable timing give the total in-rush current and the virtual-rail voltage over time. Run `perform analysis -lowpower` (RH) after the usual power and extraction steps, then read `virtual_domain_total_i.rpt` (RH) for current and `virtual_domain_worst_v.rpt` (RH) for the ramp.
A waking domain draws its in-rush current through the same straps, vias and bumps that feed the always-on logic around it, so neighbours see a dynamic drop exactly while they may be busy. Check it with a RedHawk ramp-up run in mixed mode, where `setup analysis_mode lowpower` (RH) is combined with `perform analysis -dynamic` (RH), and judge the always-on region during the wake window, not just the switched domain.
DFT insertion creates new ports and nets that cross power domains, and the functional isolation strategies often do not cover them. Run `check_isolation_coverage -dft_signals` (ICC2) to list the violating scan paths with suggested strategies, then fix them one of two ways: add strategies and rerun `insert_dft` (ICC2), or add incremental `set_dft_isolation` (ICC2) rules and apply them with `commit_dft_isolation` (ICC2).
A PVT mismatch means a cell is linked to a library pane whose process, voltage or temperature does not match the operating condition of the supplies it sits on, such as a level shifter characterized at 1.0 V in and out sitting on a 0.9 V input rail. ICC2 picks power management cells by the rule in `opt.common.pvt_setting` (ICC2); `report_pvt` (ICC2) marks which of P, V or T is off, and `fix_mv_design -verbose` (ICC2) reports PVT violations on buffers, inverters, tie cells and diodes.
Match the activity source to the question you are answering: default toggle rates for early budgets, SAIF from realistic use-case simulation for average power, and a VCD window around the worst event for peak power. Then pick the corner that makes that number worst, which is the fast, high-voltage, hot corner for leakage and the highest mode voltage for dynamic power.
Synthesis power has an ideal clock, estimated wire capacitance and often different activity, so it is expected to read low. Find the gap by running both netlists through the same corner and activity file and comparing `report_power -groups` (PT) group by group, then check clock network, wire capacitance, glitch, annotation and leakage in turn, one cause at a time.
Successive refinement means power intent grows in layers: the IP provider writes constraint UPF, the integrator adds configuration such as strategies and control signals, and implementation adds supplies and cell detail. Each later layer refines earlier commands with **-update** instead of rewriting them, so an IP's constraints travel unchanged into every chip that uses it.
When one driver fans out to loads on different supplies, a port-based strategy cannot say which branch needs isolation, so you describe it by supplies: **-source**, **-sink** and **-diff_supply_only** on `set_isolation` (UPF) put cells only on branches whose load supply differs from the driver. Nets driven by literal constants count as real drivers with a related supply, and ICC2 can skip isolation where the constant already equals the clamp value.
ICC2 resolves overlapping retention strategies by granularity, not by the order you wrote them: an explicitly named register beats a Verilog process or always block, which beats an instance, which beats a strategy that names only the domain. A -no_retention strategy outranks a retaining one, but a finer retaining strategy still wins over a coarser -no_retention, and a true tie goes to the strategy created first.
Wrong values after wake-up almost always come from the control sequence or the retention supply, not the flop. Check in order that the retention supply stayed on, that RESTORE came after the primary rail was stable and before clocks restarted, that save and restore polarity match the cells, and, for zero-pin retention cells, that `check_lp -stage design` (VCLP) reports no RET_CLAMP_INVERT.
Shutdown runs stop clocks, assert isolation, save state, then switch off and wait for the acknowledge. Wake-up is the mirror: switch on and wait for the acknowledge, restore state, release isolation, then restart clocks, and swapping any two neighbouring steps either corrupts retained state or lets unknown values reach always-on logic.
Well biasing drives the n-wells and p-wells from dedicated supplies instead of the rails, which shifts transistor threshold voltage: reverse bias cuts leakage and forward bias buys speed. In ICC2 you turn on the UPF-based bias mode with the enable_bias design attribute, supply sets in bias scopes then gain nwell and pwell functions that connect implicitly to bias PG pins, and `check_mv_design` (ICC2) enforces the bias rules.