Why check clock transition before CTS?

Short Answer

Clock transition (slew) is just the rise/fall time at a clock pin — how fast the signal ramps from low to high or high to low — and it directly drives cell delay calculation for every gate the clock touches. Before CTS exists, there's no real clock tree with real buffers driving real wire capacitance, so any transition value you see pre-CTS is an assumed input, typically set via set_clock_transition, not something measured from actual routed geometry.

Technical Explanation

• Why bother checking it at all, then? Because that assumed transition feeds every downstream delay calculation in pre-CTS timing analysis — if the assumption is unrealistically fast (say, 50ps when a real clock buffer chain would realistically deliver 150–200ps), your pre-CTS timing will look artificially clean and then blow up in surprise violations once CTS builds the real tree.
• It's also a sanity check against the library: an assumed transition that violates the library's own max_transition characterization range is a red flag that someone picked an unrealistic number rather than one grounded in typical clock buffer sizing for this technology.
• Practically, teams often calibrate this assumption based on prior tapeouts in the same node/library — "our clock trees in this technology typically settle around X ps of transition at the leaf" — rather than guessing.
• Once CTS runs and clocks propagate, this assumed value is replaced by the real, calculated transition at every clock pin — so this check is specifically a pre-CTS sanity gate, not something you keep worrying about afterward.

What To Check

• Warning sign: The design uses an unrealistic default or a post-CTS value copied from another block.
• Inspect: Compare one named object across the related reports; the same object should tell a consistent story.
• Correct: Apply the characterised methodology assumption and keep it distinct from later propagated results.

Healthy, Suspicious & Hard-stop Results

• Expected: An explicit pre-CTS transition can be a modelling assumption for cell delay; it is not a measured routed-clock slew.
• Stop before floorplanning when required logic or timing coverage is missing or unexplained.

What The Interviewer Is Testing

Be ready to explain why this matters before floorplanning.

Follow-up Question & Model Response

Model response: “I would save the report, inspect one affected object in the correct block and scenario, and make or request this correction. ”