IntermediateQuestion 2 of 222

What clock information must be available before physical design?

From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

Before PD can start, you need a complete "clock passport" for the design: every real clock source (PLL outputs, crystal-derived clocks, external clock pins), every generated clock (dividers, multipliers) and its exact relationship to its master clock, and the waveform/uncertainty assumptions that apply in each operating mode. A generated clock isn't automatically asynchronous to its parent just because it's divided — the master/source/edge relationship has to be explicitly declared [SDC: create_generated_clock -source -divide_by, etc.] so STA compares the right launch and capture edges; get this wrong and you'll either miss real timing paths or create phantom violations on paths that are actually safe.

Technical Reference DiagramWhat clock information must be available before physical design?

Technical Explanation

  • Before PD can start, you need a complete "clock passport" for the design: every real clock source (PLL outputs, crystal-derived clocks, external clock pins), every generated clock (dividers, multipliers) and its exact relationship to its master clock, and the waveform/uncertainty assumptions that apply in each operating mode.
  • A generated clock isn't automatically asynchronous to its parent just because it's divided — the master/source/edge relationship has to be explicitly declared [SDC: create_generated_clock -source -divide_by, etc.] so STA compares the right launch and capture edges; get this wrong and you'll either miss real timing paths or create phantom violations on paths that are actually safe.
  • Remember: CTS builds the physical clock tree, but it does not invent the functional clock spec. If the SDC is missing a generated clock or has the wrong relationship, CTS will happily synthesize a tree for whatever's declared — silently building the wrong thing.
  • Pre-CTS, expect the clock network to be modeled as largely ideal — you supply set_clock_latency and set_clock_uncertainty as stand-ins for real insertion delay and skew, which only become measurable after clock implementation, when they're marked propagated.
  • When you do transition from ideal to propagated, do it deliberately — don't leave both an estimated latency margin AND the newly measured propagated skew active simultaneously, or you're double-counting the same physical effect twice.
  • Also confirm clock gating and test-mode MUX controls are correctly modeled per mode: missing generated clocks on gated branches can leave whole register groups with no real timing check applied, and sloppy set_clock_groups/false-path exceptions can accidentally mask legitimate clock-domain-crossing paths instead of correctly excluding only the truly false ones.
  • Don't just eyeball a list of clock names — pull report_clock and spot-check representative timing paths end-to-end to confirm the declared relationships actually produce the checks you expect.

Command Checks & Actions

PrimeTime (SDC)create_clock -name clk -period 2.0 -waveform {0 1.0} [get_ports clk]

Defines the primary/master clock that everything else in the clock tree ultimately derives from.

PrimeTime (SDC)create_generated_clock -name gclk -source [get_pins masterclk] -divide_by 2 [get_pins div/Q]

Defines a derived clock through logic such as a divider. If the master clock never actually reaches the declared -source pin, the generated clock is "not expanded" and effectively unusable -- one of the most common constraint bugs in a clock setup.

PrimeTimeanalyze_clock_networks -traverse_disabled

Traces exactly where clock propagation stops and why -- the standard way to debug a generated clock that never expanded, rather than guessing from the SDC text alone.

Common Mistake

The Trap: Declaring every different clock name asynchronous, or assuming CTS repairs missing clock constraints.

Follow-up Question & Model Response

"What would you check if registers behind a divider are unconstrained?"

Candidate Model Response: Check the divider output, generated-clock definition, source/master selection, and propagation through the active mode.

Practical Example

Tapeout Scenario: A divide-by-two output derived from a 10 ns source has a 20 ns period, but its phase and edge relationship still matter. Defining it as an unrelated primary clock can discard useful relationship information.

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IntermediateWhat scan and DFT information is needed for physical design?IntermediateWhat must be true before a design is ready to hand off from placement to CTS?BeginnerWhat is SDC, and what should a physical-design SDC contain?ExpertWhat is CCD (Concurrent Clock and Data optimization), and what does it actually change in the clock tree?