IntermediateQuestion 48 of 222

How do you audit input-delay min and max completeness?

From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide

Short Answer

Every timed input port needs both a min and a max input delay โ€” skipping one isn't "conservative by default," it just leaves that side of the timing check unconstrained. Max input delay models the latest possible external arrival, which drives setup analysis at the internal capture flop; min input delay models the earliest possible arrival, which drives hold analysis.

Technical Reference DiagramHow do you audit input-delay min and max completeness?

Technical Explanation

  • Both values must reference the correct clock and the correct edge โ€” an input delay pointing at the wrong clock domain, or the wrong edge of the right clock, produces numbers that look plausible but constrain the wrong thing entirely.
  • Also check rise/fall scope: if the interface has asymmetric rise/fall timing (common with some I/O standards), a single "same for both edges" input delay can under-constrain one transition direction.
  • For ports where the true early/late interface behavior differs meaningfully, use explicit separate min/max values rather than a single value applied to both โ€” a lazy single-value assignment is a common source of missed hold violations at chip boundaries.
  • Audit systematically: walk every timed input port and confirm min, max, reference clock, and edge are all explicitly set and correct โ€” don't rely on "it's probably fine" for boundary timing, since input/output interface bugs are notoriously hard to catch late.

What To Check

  • Warning sign: Only max delay exists, so setup is analysed while hold coverage is incomplete.
  • Inspect: Compare one named object across the related reports; the same object should tell a consistent story.
  • Correct: Return to the interface budget and add the missing intentional cases; do not duplicate max blindly as min.

Command Checks & Actions

  • report_ports -input_delay [get_ports *]: shows boundary constraints and electrical assumptions
  • check_timing: finds missing or inconsistent timing setup

Run the commands in order. Each line answers a separate part of the check.

Healthy, Suspicious & Hard-stop Results

  • Expected: For each timed input, confirm reference clock, edge, rise/fall scope, and both early and late interface intent where required.
  • Stop before floorplanning when required logic or timing coverage is missing or unexplained.

Common Mistake

The Trap: Do not assume the check passed just because ICC2 continued. Fix or narrowly justify the named objects, then rerun the same command.

What The Interviewer Is Testing

Be ready to explain why this matters before floorplanning.

Follow-up Question & Model Response

Model response: โ€œI would save the report, inspect one affected object in the correct block and scenario, and make or request this correction. โ€

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