What are TLUPlus and RC technology files, and why is a layer map needed?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
Cell timing models tell you how a gate behaves, but they say nothing about the wires connecting gates — and wire geometry adds both delay and load, so you need a separate model for that. A wire's electrical behavior depends on its shape and its neighbors: a long, thin wire behaves very differently from a short, wide one, and a nearby parallel conductor changes its effective capacitance.
Technical Explanation
- Cell timing models tell you how a gate behaves, but they say nothing about the wires connecting gates — and wire geometry adds both delay and load, so you need a separate model for that.
- A wire's electrical behavior depends on its shape and its neighbors: a long, thin wire behaves very differently from a short, wide one, and a nearby parallel conductor changes its effective capacitance.
- Before routing exists, the flow has to estimate interconnect; after routing, real geometry is available and can be extracted properly — TLUPlus is the layer-specific parasitic model ICC2's native extraction engine reads via
read_parasitic_tech, then associates with a specific corner viaset_parasitic_parameters. Those are two separate actions — reading a model doesn't automatically select it for use. - Here's the trap: if the technology file calls a layer "M1" but the TLUPlus model calls the same physical layer "METAL1," you need a validated layer map to connect the two names — and that map is not a license to mix different process stacks; the underlying physical layers still have to actually correspond. Always check conducting layers, vias, units, and which corner the model targets before trusting the mapping.
Command Checks & Actions
read_spef design.spefLoads extracted parasitics -- the actual per-net RC data whose accuracy depends entirely on the TLUPlus layer map used at extraction time.
report_annotated_parasiticsReports which nets actually got real extracted RC data versus falling back to an estimate, which is exactly what a missing or mismatched layer map would cause.
Common Mistake
The Trap: Loading two files and assuming ICC2 has automatically assigned them to all intended timing corners.
Follow-up Question & Model Response
"How do you separate a layer-map issue from a bad timing constraint?"
Candidate Model Response: Check extraction/model diagnostics and actual RC assignments before changing the SDC.
Practical Example
Tapeout Scenario: A setup corner might select an approved late RC model while a hold calculation uses an approved early model. The correct combinations come from the signoff matrix; RCmax is not a universal synonym for the worst case of every path.
PnR Flow Mentor Guide
Master the Physical Design Implementation Flow
Read the complete 8-chapter PnR Flow Mentor Guide free on the web — library setup through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO, all the way to stream-out.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.
Continue practising