What is SDC, and what should a physical-design SDC contain?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
SDC is the design's stated timing contract: which clocks exist, which paths matter, and under what electrical assumptions they get checked. A solid handoff SDC defines primary and generated clocks with real periods and waveforms, input/output delay budgets, sensible transition or driving-cell/load assumptions at the boundary, and any timing exceptions — with justification, not just wildcards.
Technical Explanation
- SDC is the design's stated timing contract: which clocks exist, which paths matter, and under what electrical assumptions they get checked.
- A solid handoff SDC defines primary and generated clocks with real periods and waveforms, input/output delay budgets, sensible transition or driving-cell/load assumptions at the boundary, and any timing exceptions — with justification, not just wildcards.
- Syntactically valid SDC can still select the wrong objects: a port renamed during synthesis means a command runs without error but silently selects nothing, and overly broad wildcards can constrain things you never intended.
- So don't just check that the file parses — read the tool's messages and actually inspect which clocks, endpoints, and exceptions resulted.
- ICC2 ties constraints to modes, corners, and scenarios, so a flat SDC pulled from another tool usually needs real conversion, not a blind copy-paste into every scenario.
- Remember that a timing report only describes the constrained problem you gave the tool — it doesn't tell you whether that matches the designer's actual intent.
Visual Verification
Synopsys Design Constraints (SDC) formalize the timing contract across registers, establishing clock periods, jitter uncertainty margins, I/O delay budgets, and path exceptions that drive physical optimization.
Command Checks & Actions
create_clock -name clk -period 8.0 -waveform {0.0 4.0} [get_ports clk]Defines the clock, the first thing a physical-design SDC has to establish before anything downstream can be timed.
check_timingFlags missing or inconsistent timing setup. This is the command that actually verifies an SDC is complete, separate from whether it merely loaded without a syntax error.
report_exceptionsLists every false-path, multicycle, and max-delay exception currently loaded, so the SDC's actual exception set can be checked against what was intended rather than assumed.
Common Mistake
The Trap: Equating SDC with only create_clock, or claiming that zero reported timing violations means every path is constrained.
Follow-up Question & Model Response
"What proves an SDC was applied correctly?"
Candidate Model Response: Reports of actual clocks, constrained interfaces, exceptions, and coverage in each required scenario.
Practical Example
Tapeout Scenario: A 10 ns clock describes a nominal 100 MHz period. It does not tell the tool when data arrives at an input or how much time an external receiver needs after an output. Those interfaces require additional constraints.
PnR Flow Mentor Guide
Master the Physical Design Implementation Flow
Read the complete 8-chapter PnR Flow Mentor Guide free on the web — library setup through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO, all the way to stream-out.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.
Continue practising