IntermediateQuestion 49 of 222

Why should input delay not be applied indiscriminately to clock ports?

From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide

Short Answer

A clock port isn't ordinary launched data — it's the time reference that every other path in the design is measured against, so treating it like any other input is a category error, not just a minor constraint mistake. set_input_delay says "this signal arrives relative to some clock, with this much delay" — but applying that to the clock signal itself creates a circular, nonsensical statement: you'd be defining the clock's arrival relative to itself (or another clock) as if it were ordinary data.

Technical Reference DiagramWhy should input delay not be applied indiscriminately to clock ports?

Technical Explanation

  • The classic way this bug slips in is a broad, careless selector — something like set_input_delay ... [get_ports *] — which happily sweeps up your clock ports along with your real data inputs, because the wildcard doesn't know the difference.
  • The consequence isn't a clean error; it's nonsensical downstream timing arcs and confusing violations that don't trace back cleanly to a root cause, because the tool is now trying to reconcile a clock definition with a conflicting data-delay constraint on the same port.
  • g. [remove_from_collection [all_inputs] [get_ports clk]] or an equivalent filter), and treat any SDC script using unfiltered wildcards on ports as a code-review flag.

What To Check

  • Warning sign: A blanket input-delay command constrains clocks and resets as data.
  • Inspect: Compare one named object across the related reports; the same object should tell a consistent story.
  • Correct: Select intended data ports explicitly and review collection membership before applying delays.

Command Checks & Actions

  • get_ports *: selects boundary ports
  • report_ports -input_delay [get_ports *]: shows boundary constraints and electrical assumptions

Run the commands in order. Each line answers a separate part of the check.

Healthy, Suspicious & Hard-stop Results

  • Expected: A clock port defines timing reference behaviour and is not ordinary launched data; bulk get_ports * selectors can impose nonsensical data delay.
  • Stop before floorplanning when required logic or timing coverage is missing or unexplained.

Common Mistake

The Trap: Do not assume the check passed just because ICC2 continued. Fix or narrowly justify the named objects, then rerun the same command.

What The Interviewer Is Testing

Be ready to explain why this matters before floorplanning.

Follow-up Question & Model Response

Model response: “I would save the report, inspect one affected object in the correct block and scenario, and make or request this correction. ”

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