What are fin pitch, gate pitch, and contacted gate pitch in a FinFET technology?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
These three numbers all sound similar and all get reported in nanometers, but they're measuring completely different physical directions and features — mixing them up is a common and costly mistake when reading a process datasheet. Fin pitch measures center-to-center spacing between neighboring fins — the vertical silicon "fins" that run in one direction across the device.
Technical Explanation
- These three numbers all sound similar and all get reported in nanometers, but they're measuring completely different physical directions and features — mixing them up is a common and costly mistake when reading a process datasheet.
- Fin pitch measures center-to-center spacing between neighboring fins — the vertical silicon "fins" that run in one direction across the device.
- Gate pitch measures the repeat spacing between neighboring gate lines — which run perpendicular to the fins in a typical layout. Because these are orthogonal directions, gate pitch and fin pitch describe entirely different geometric features, even though both show up in the same cross-section.
- Contacted gate pitch (CPP) is a gate-repeat metric too, but it specifically includes the space needed for the source/drain contact arrangement — it's not just "gate to gate," it's "gate to gate accounting for what has to fit between them electrically."
- A gate's drawn channel length (along the current-flow direction) is yet another distinct dimension from the spacing between adjacent gates — don't conflate "how long is one gate" with "how far apart are two gates."
- Here's the trap: process-node marketing names (like "7nm") are not reliable stand-ins for any of these actual measured pitches — always go to the real characterized numbers.
- And critically for PD work: fin count and CPP influence device density and constrain library cell layout, but they don't by themselves determine standard-cell area or routability — contacts, diffusion breaks, power rails, local interconnect, and pin access all consume real space too. When you look at an ICC2 FinFET placement grid report with separate X/Y pitch and offset values, don't assume X pitch = CPP or Y pitch = fin pitch unless your technology's methodology documentation explicitly says so.
Command Checks & Actions
set_technology -node 7Applies the node's fin pitch, gate pitch, and contacted gate pitch as part of the technology setup -- these are technology-file constants, not values computed at runtime.
create_exterior_tap_walls -lib_cell <cell> -side <side> -bbox {{llx lly} {urx ury}}Its own placement constraint -- a horizontal wall cell's width must be an integer multiple of the FinFET x-pitch -- makes the fin-pitch grid concrete and directly checkable rather than abstract.
Common Mistake
The Trap: Using “fin pitch,” “gate length,” “CPP,” and “FinFET placement grid” as interchangeable terms.
Follow-up Question & Model Response
"Why should a PNR engineer care about transistor-level pitches?"
Candidate Model Response: They help explain library quantization and boundary restrictions, but placement legality must still use the delivered tool/library rules.
Practical Example
Tapeout Scenario: In an invented teaching layout, fins repeat every 40 nm and gates repeat every 70 nm. Those two measurements do not imply 40 nm wire width, 70 nm gate length, or a specific process-node name.
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