What files and information are required for SRAMs and other hard macros?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
A macro handoff isn't one file — it's a package: physical abstraction (size, pin shapes, obstructions) for placement/routing, timing views for interface behavior across every required operating condition, and a functional model for simulation or equivalence checks. A netlist black box with no supporting views is not a complete handoff — it's a placeholder that will silently break downstream analysis the moment someone assumes it's real data.
Technical Explanation
- A macro handoff isn't one file — it's a package: physical abstraction (size, pin shapes, obstructions) for placement/routing, timing views for interface behavior across every required operating condition, and a functional model for simulation or equivalence checks.
- A netlist black box with no supporting views is not a complete handoff — it's a placeholder that will silently break downstream analysis the moment someone assumes it's real data.
- Memories carry operating assumptions beyond plain timing: clocks, setup/hold checks, read/write behavior, test-mode controls, power pins, legal orientations, and sometimes multiple supply rails — plus integration guidance like keepouts or routing restrictions around the macro.
- Don't trust a familiar macro name — verify the memory compiler configuration, depth, width, mux option, and revision match, confirm instantiated cell/pin names line up, and make sure timing models actually exist for every scenario you'll analyze. A dimensionally-correct abstract with the wrong pin arrangement is physically dangerous; a timing view pulled from a different memory configuration is electrically misleading.
Command Checks & Actions
create_lib -ref_libs {../SRAM/sram.ndm}Attaches the hard macro's NDM as a single reference library -- its physical view (equivalent to LEF) plus its .lib timing view arrive together as one package.
report_ref_libsConfirms the macro's reference library actually carries technology/physical info rather than just a timing stub, which is the difference between a macro you can floorplan and one you can only time.
Common Mistake
The Trap: Candidates often mistakenly saying that a macro's LEF alone is enough for timing-driven implementation, or that GDS replaces its timing model.
Follow-up Question & Model Response
"What would you request for an intentionally untimed block?"
Candidate Model Response: An explicit approved timing abstraction or exception methodology, plus physical and interface data; do not silently waive missing models.
Practical Example
Tapeout Scenario: A 512-by-32 SRAM and a 1024-by-32 SRAM may have similar names but different sizes and timing. Using one macro's abstract with the other's timing model does not produce a valid combined cell.
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