How is an RC technology file different from SPEF?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
Think of an RC technology file (like TLUPlus) as a recipe for calculating parasitics, reusable across any design on that process — SPEF is the finished dish: the actual extracted parasitic values for one specific design's nets. The extractor combines the technology recipe with your design's real layout geometry to produce that design-specific result, complete with net names, connections, and R/C values in whatever naming and unit convention the receiving timing flow needs to interpret correctly.
Technical Explanation
- Think of an RC technology file (like TLUPlus) as a recipe for calculating parasitics, reusable across any design on that process — SPEF is the finished dish: the actual extracted parasitic values for one specific design's nets.
- The extractor combines the technology recipe with your design's real layout geometry to produce that design-specific result, complete with net names, connections, and R/C values in whatever naming and unit convention the receiving timing flow needs to interpret correctly.
- Because SPEF is tied to actual routed geometry, it goes stale the moment the route changes — even though the underlying process model (TLUPlus) hasn't changed at all.
- A finished SPEF usually isn't a mandatory day-one input for a fresh P&R run (there's no route yet to extract from), but it becomes relevant for a restart, a hierarchical timing model, or feeding a downstream STA flow — and whenever parasitics get handed off, verify the design revision, extraction corner, units, hierarchy/bus-name mapping, and actual annotation coverage; a file that parses cleanly doesn't guarantee every intended net actually got annotated.
Command Checks & Actions
read_spef design.spefLoads the per-net extracted RC data (SPEF) -- the actual output of extraction, as opposed to the TLUPlus rules that produced it.
report_annotated_parasiticsConfirms which nets are back-annotated from real SPEF data versus an estimate, making the TLUPlus-vs-SPEF distinction (rules vs. results) checkable rather than just definitional.
Common Mistake
The Trap: Candidates often mistakenly calling TLUPlus a chip-specific wire-delay report, or requiring final SPEF before initial placement can begin.
Follow-up Question & Model Response
"What is the first question when SPEF timing differs unexpectedly?"
Candidate Model Response: Confirm that the netlist, layout revision, corner, and annotation coverage correspond to the same design state.
Practical Example
Tapeout Scenario: Routing a net around a newly placed SRAM can lengthen it. Its extracted SPEF network should then change, while the approved RC technology model may remain identical. Reusing an old SPEF can silently analyze the old route.
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