How is RTL different from the netlist used for place and route?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
RTL is intent — "add these two registers" — while the netlist is the actual implementation synthesis chose: specific gates, specific drive strengths, specific structures. RTL alone can't tell you which adder topology or cell variants got used; only the mapped netlist exposes the real instances and connectivity that physical design can place and route.
Technical Explanation
- RTL is intent — "add these two registers" — while the netlist is the actual implementation synthesis chose: specific gates, specific drive strengths, specific structures.
- RTL alone can't tell you which adder topology or cell variants got used; only the mapped netlist exposes the real instances and connectivity that physical design can place and route.
- That's why a bare cell reference like NAND2_X1 is meaningless without its matching library view — no size, no delay, nothing to place.
- A design can simulate perfectly at RTL and still be unready for PD: functional correctness at RTL says nothing about missing library references, incompatible macros, or incomplete SDC in the mapped netlist.
- At handoff, cross-check the RTL/synthesis revision the team recorded against the netlist revision you actually received, and confirm whether scan insertion and low-power transforms already happened.
- The ICC2 import flow described here expects structural Verilog — don't hand it behavioral RTL and expect the same result.
Visual Verification
RTL specifies behavioral logic intent (such as "+" addition) without gate sizing, whereas the mapped netlist realizes this intent using discrete library cells with defined drive strengths and pin interfaces.
Command Checks & Actions
read_verilog design.vLoads the mapped gate-level netlist PnR actually consumes. RTL itself is never read by the PnR tool -- by the time a design reaches ICC2 it has already been through synthesis.
link_block -rebindConfirms every loaded instance is a real library cell -- a check that is only meaningful on a post-synthesis netlist, since RTL has no library cells to resolve against.
Common Mistake
The Trap: Candidates often mistakenly claiming that physical design only moves cells and never changes the mapped circuit. Optimization can make implementation changes that require equivalence validation.
Follow-up Question & Model Response
"Which input would you inspect for a wrong drive-strength cell name?"
Candidate Model Response: Inspect the mapped netlist and the synthesis library manifest together.
Practical Example
Tapeout Scenario: Two libraries can map the same RTL addition into different cell networks. A netlist built against library A may contain cells absent from library B, so swapping the library directory is not a safe technology migration.
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