How should undriven and unloaded objects be reviewed?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
A driver produces a signal; a load consumes it. An undriven object has no valid source feeding it, and an unloaded output has nowhere meaningful to go. Neither is automatically a bug — both can be legitimate at a design boundary (an unused output pin, an intentionally tied-off input) or they can be evidence that connectivity got lost somewhere during synthesis or netlist editing.
Technical Explanation
- Review each one individually against what the design boundary and intent actually call for, rather than blanket-ignoring or blanket-flagging the whole list.
Visual Verification
Undriven input pins cause undefined high-Z logic states and shoot-through current, whereas unloaded outputs waste dynamic power and area unless designated as spare cells.
What To Check
- Warning sign: A control pin floats or a functional output disappeared during synthesis.
- Inspect: Start with one named object in the report and trace it to the netlist, library, or SDC statement that created it.
- Correct: Trace hierarchy and port intent, obtain an upstream repair when functional connectivity is wrong, and document genuine unused interfaces.
Command Checks & Actions
- check_netlist: reports structural connectivity problems
- report_ports -verbose [get_ports *]: shows boundary constraints and electrical assumptions
Run the commands in order. Each line answers a separate part of the check.
Healthy, Suspicious & Hard-stop Results
- Expected: An undriven object lacks a valid source; an unloaded output drives nothing. Either can be intentional at a boundary or evidence of lost connectivity.
- Stop before floorplanning when required logic or timing coverage is missing or unexplained.
Common Mistake
The Trap: Do not assume the check passed just because ICC2 continued. Fix or narrowly justify the named objects, then rerun the same command.
What The Interviewer Is Testing
Be ready to explain why this matters before floorplanning.
PnR Flow Mentor Guide
Master the Physical Design Implementation Flow
Read the complete 8-chapter PnR Flow Mentor Guide free on the web — library setup through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO, all the way to stream-out.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.
Continue practising