Which logical counts should be reconciled?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
Think of this as taking inventory after a shipment arrives — you're not re-verifying every connection, you're checking that the counts on the packing slip match what actually showed up. Compare ports, hierarchical cell instances, sequential cell counts, combinational cell counts, memory/macro counts, net counts, and unresolved reference counts against what the synthesis handoff reported.
Technical Explanation
- These counts are fingerprints, not proofs — a perfect count match doesn't guarantee the design is functionally correct, but a large mismatch is an immediate, cheap signal that something is wrong before you invest time in deeper analysis.
- A big divergence in any one category tells you where to look: a sequential-cell-count mismatch points at scan insertion or flop-related logic, a macro-count mismatch points at IP integration, an unresolved-reference count above zero points at a broken link/import.
- Do this reconciliation right after import/linking — it's the cheapest possible sanity check and catches the "wrong revision loaded" or "wrong hierarchy resolved" class of bug before it wastes hours of downstream debugging.
- Pair this with checksums and manifest review — checksums confirm a file didn't change, design-statistics reconciliation confirms the content that was loaded matches what was expected, and you need both because a technically-unchanged file can still be the wrong file for this handoff.
Visual Verification
Inventory reconciliation verifies exact correspondence between synthesized cell counts and imported database objects, exposing unlinked sub-blocks or accidentally dropped hierarchies.
What To Check
- Warning sign: A large count mismatch reveals the wrong top, a missing hierarchy, or different optimisation settings.
- Inspect: Start with one named object in the report and trace it to the netlist, library, or SDC statement that created it.
- Correct: Identify the first mismatching class and resolve the revision or import cause before timing review.
Command Checks & Actions
- sizeof_collection [get_ports *]: counts exactly the objects returned by a selector
- sizeof_collection [get_cells -hierarchical *]: counts exactly the objects returned by a selector
- sizeof_collection [get_nets -hierarchical *]: counts exactly the objects returned by a selector
Run the commands in order. Each line answers a separate part of the check.
Healthy, Suspicious & Hard-stop Results
- Expected: Compare ports, hierarchical cells, sequential cells, combinational cells, memories/macros, nets, and references with the synthesis handoff.
- Stop before floorplanning when required logic or timing coverage is missing or unexplained.
Common Mistake
The Trap: Do not assume the check passed just because ICC2 continued. Fix or narrowly justify the named objects, then rerun the same command.
What The Interviewer Is Testing
Be ready to explain why this matters before floorplanning.
PnR Flow Mentor Guide
Master the Physical Design Implementation Flow
Read the complete 8-chapter PnR Flow Mentor Guide free on the web — library setup through placement, clock tree synthesis, routing, chip finishing, hierarchical implementation, and ECO, all the way to stream-out.
Offline PDF Bundle
Want all 1109 questions offline?
Get the complete 4-book PDF bundle (PnR, STA, MMMC, Low Power) with a clickable table of contents - no ads, no internet needed.
Continue practising