What is Placement Cell Padding, and how does it relieve routing congestion?
From PDVerse PnR Interview Handbook, part of the pdVerse Mentor Guide
Short Answer
Complex standard cells — AOI22s, OAI33s, wide MUXes, scan flops — pack a lot of pins into a small footprint, and when several of them abut directly, their combined pin demand can exceed what the local metal layers can route, causing shorts. Padding is a placement-time trick: tell the tool to treat a cell as wider than it physically is (e.g., a 4-site cell padded to look 6 sites wide), reserving empty "halo" sites on either side that no other cell may occupy.
Technical Explanation
- Complex standard cells — AOI22s, OAI33s, wide MUXes, scan flops — pack a lot of pins into a small footprint, and when several of them abut directly, their combined pin demand can exceed what the local metal layers can route, causing shorts.
- Padding is a placement-time trick: tell the tool to treat a cell as wider than it physically is (e.g., a 4-site cell padded to look 6 sites wide), reserving empty "halo" sites on either side that no other cell may occupy.
- You can apply padding globally to every instance of a troublesome library cell (master padding), or surgically to just the specific instances sitting in a known-congested region (instance padding).
- Padding is strictly a placement-time fiction — once routing starts, the virtual halo disappears, leaving genuinely empty, legal routing tracks behind for metal jumpers to use.
Common Mistake
The Trap: Applying 4-site padding globally to every standard cell in the design. This inflates the design area, causes artificial floorplan utilization overflow, and pushes timing-critical cells too far apart.
Follow-up Question & Model Response
"What is the difference between a hard placement blockage and cell padding?"
Candidate Model Response: A placement blockage forbids all cell placement inside a fixed bounding box. Cell padding moves with the cell instance, keeping an empty clearance halo around that specific cell.
Practical Example
Applying Master & Instance Cell Padding:
# Synopsys ICC2: Add 1-site left and right padding to all AOI/OAI cells
set_lib_cell_padding -left_site 1 -right_site 1 [get_lib_cells */AOI* */OAI*]
# Add instance-level padding to specific congested ALU registers
set_cell_padding -left_site 2 -right_site 2 [get_cells u_alu/reg_*]PnR Flow Mentor Guide
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