How do you constrain a port that receives paths from multiple clocks, and why is -add_delay needed?
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Specify each clock's delay on the port with -add_delay (SDC). Without it, a new set_input_delay/set_output_delay on a port removes the port's existing delay data and replaces it, so a second command without the flag would silently wipe out the first clock's budget instead of adding to it.
Technical Explanation
When paths from more than one clock, or more than one edge of one clock, arrive at the same port, each launching condition needs its own budget on that port โ and -add_delay (SDC) is the mechanism for accumulating them.
- Why the flag is mandatory, not stylistic: by default, a new
set_input_delayorset_output_delayon a port removes whatever delay data already exists there and replaces it entirely. - What happens without it: writing a second clock's delay on the same port with no
-add_delaydoesn't add a second budget โ it silently discards the first one, leaving that port constrained relative to only the most recent clock. - What happens with it: the new delay sits alongside the existing ones, so the port ends up constrained relative to every relevant clock at once.
- A worked pair:
set_input_delay 4.5 -clock PHI1 {IN1}followed byset_input_delay 2.3 -clock PHI2 -add_delay {IN1}givesIN1delays relative to bothPHI1andPHI2; the same second command without-add_delaywould have erased thePHI1delay entirely. - The same rule applies within one clock:
set_input_delay 4.5 -clock PHI1 -max -rise -add_delay {IN1}andset_input_delay 4.0 -clock PHI1 -max -fall -add_delay {IN1}accumulate the rise and fall budgets rather than one overwriting the other. - When this actually matters: whenever a port genuinely receives data launched by different clocks, different edges, or different modes โ each distinct launching condition needs its own preserved budget.
Common Mistake
The Trap: writing a second set_input_delay on a shared port without -add_delay, assuming SDC commands are additive by default.
- A designer constrains a multiplexed port against
PHI1first, then later adds aPHI2constraint for a second clock domain feeding the same port, without noticing the second command has no-add_delay. - The
PHI1constraint silently disappears, so every path launched relative toPHI1through that port is now checked with no input delay at all โ a constraint gap that produces optimistic timing rather than any visible error.
Follow-up Question & Model Response
How would you verify, on an existing SDC file, that a port meant to carry delays from two clocks actually has both, rather than one that got silently overwritten?
Candidate Model Response: Run report_port -input_delay [get_ports IN1] (PT), which lists every currently active input delay on that port along with the clock each one is relative to. If only one clock's delay shows up where two were intended, that's the signature of a missing -add_delay on the second command. Grepping the SDC source for every set_input_delay targeting that port and confirming every command after the first one carries -add_delay is the faster static check before even running the tool.
Practical Example
Port IN1 on a bridge block receives data launched by both a 250 MHz PHI1 domain and a 100 MHz PHI2 domain through a shared input mux. The SDC has set_input_delay 4.5 -clock PHI1 {IN1} (SDC) followed later by set_input_delay 2.3 -clock PHI2 -add_delay {IN1} (SDC). report_port -input_delay [get_ports IN1] confirms two entries, one per clock. Removing -add_delay from the second line and rerunning the same report shows only the PHI2 entry, with the PHI1 delay gone entirely.
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