Level 2: Construction & Debugging

Intermediate STA Interview Questions

Connect setup and hold math, clock behavior, exceptions, design rules, reporting, and practical debug.

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Connect setup and hold math, clock behavior, exceptions, design rules, reporting, and practical debug.

  1. 01 Explain the complete setup check for a register-to-register path, including which path delays are used.Intermediate: A setup check compares the latest possible data arrival at the capture flop's D pin against the earliest possible required time. Arrival is the launch clock delay plus the launch flop's clock-to-Q delay plus the slowest data path; required is one clock period plus the fastest capture clock delay, minus the flop's setup time and the clock uncertainty margin. The path passes when arrival is less than or equal to required.
  2. 02 Explain the complete hold check and why a long clock path can cause a hold violation.Intermediate: A hold check verifies that data launched by a clock edge does not race through the logic and corrupt the value that same edge is supposed to capture from the previous cycle. Unlike setup, no clock period is added: the tool compares the fastest data arrival against the latest capture edge, so skew and short paths decide the outcome, not the clock frequency.
  3. 03 What is clock propagation, and what does set_propagated_clock actually change?Intermediate: Before layout, STA typically assumes an ideal clock: it arrives at every flop at exactly the same time, with zero skew. `set_propagated_clock` (SDC) switches the tool to use the clock's real insertion delay through the actual clock tree built during clock tree synthesis (CTS) — the step that builds the physical wiring that distributes the clock.
  4. 05 What's the difference between clock uncertainty and clock jitter?Intermediate: Clock jitter is the clock edge itself wobbling from cycle to cycle at its source — a physical property of the clock generator (a PLL, for example) that the tool cannot derive on its own. Clock uncertainty is a margin the designer explicitly tells the tool to subtract from the setup or hold budget, using `set_clock_uncertainty` (SDC), to account for jitter plus other unmodeled effects like residual skew.
  5. 06 What's the difference between clock source latency and clock network latency, and why model them separately before CTS?Intermediate: Source latency is the delay from the clock's true origin — an off-chip pin, or a PLL — to the point in the design where the clock is defined. Network latency is the estimated on-chip delay through the clock tree itself, from that definition point to each register. Both are set with `set_clock_latency` (SDC) as stand-in numbers before clock tree synthesis has built a real tree to measure.
  6. 07 How do you constrain a DDR-style interface where data needs both -clock and -clock_fall input delays?Intermediate: A DDR (double data rate) interface launches or captures data on both the rising and falling clock edges, so one input delay referencing only the rising edge covers half the data. The `-clock_fall` option on `set_input_delay`/`set_output_delay` (SDC) tells the constraint to reference the falling edge instead, and the rising and falling constraints must be applied together, not one overwriting the other.
  7. 08 Why is a false path dangerous if the "it can never happen" assumption turns out to be wrong?Intermediate: A false path is a path the tool can trace through the netlist, but which the engineer asserts can never actually be exercised in real functional operation — for example, a path only active in a test mode that never coexists with the capturing clock. `set_false_path` (SDC) tells the tool to stop timing that path entirely, so if the assumption behind it is wrong, the path ships with zero timing verification and no warning.
  8. 10 What is the difference between asynchronous, logically_exclusive, and physically_exclusive clock groups?Intermediate: `set_clock_groups` (SDC) classifies how two clock domains relate for timing purposes. `-asynchronous` marks clocks with no fixed phase relationship, so paths between them are not meaningfully timed. `-logically_exclusive` marks clocks that never operate at the same time functionally, though they may still coexist physically on the die. `-physically_exclusive` goes further, asserting the clocks also cannot electrically interfere with each other.
  9. 11 How do you define a generated clock correctly, and what goes wrong if you use create_clock instead on a divided clock?Intermediate: A generated clock is one derived on-chip from a master clock — by a divider, a clock gate, a multiplexer, or an inverter. It must be defined with `create_generated_clock` (SDC), not `create_clock` (SDC), so the tool understands and preserves the exact phase relationship between the generated clock and the master clock it comes from.
  10. 12 What is the difference between recovery/removal checks and setup/hold checks?Intermediate: Recovery and removal are the asynchronous-control equivalents of setup and hold, but applied to a register's set or clear pin rather than its data pin. Recovery is setup-like — the control signal must be de-asserted early enough before the clock edge. Removal is hold-like — the signal must stay asserted long enough after the edge before releasing.
  11. 13 What is a max_transition violation, and why is it treated as a design rule rather than a slack-based check?Intermediate: `max_transition` is a design-rule ceiling, defined in the standard cell library, on the largest transition time — how long a signal takes to swing between logic levels — that a cell's input or output pin is allowed to see. A violation is a hard design rule check (DRC) failure, verified against a fixed library limit, independent of whether the path around it has positive timing slack.
  12. 14 What are max_capacitance limits, and is max_fanout also covered by these library references?Intermediate: `max_capacitance` (LIB) is a design-rule ceiling, specified per pin in the standard cell library, on the largest output load — the total capacitance of the wire plus whatever it drives — a cell is allowed to drive. Like `max_transition`, exceeding it is a hard DRC failure regardless of the path's timing slack. `max_fanout` (LIB) is a related but separate library attribute limiting the number of pins driven, not the electrical load directly.
  13. 15 What is timing-exception precedence, and why can a broad false path silently swallow an intended multicycle exception?Intermediate: When more than one timing exception could apply to the same path, the tool resolves the conflict by precedence rather than combining them — and `set_false_path` (SDC) takes precedence over `set_multicycle_path` (SDC). A broad false path declaration can therefore completely exclude a path an engineer meant only to relax with a multicycle exception, with no warning that the multicycle command was ever overridden.
  14. 16 What is the difference between graph-based analysis (GBA) and path-based analysis (PBA)?Intermediate: GBA keeps a single worst-case slew value at each node of the timing graph and reuses that same value for every path passing through it — fast, but pessimistic, since it can penalize a fast path with a slow, unrelated path's slew. PBA re-times each path individually using its own actual slews all the way along, which is more accurate but too computationally expensive to run on every path in the design.
  15. 17 How do you read the arc-by-arc breakdown in a report_timing output to find the dominant delay contributor?Intermediate: `report_timing` (PT) prints a Point/Incr/Path table that walks down the path arc by arc, showing each cell or net arc's own incremental delay alongside the running cumulative total. To find the dominant delay contributor, scan the Incr column for the single largest jump — not the final cumulative Path value, which only tells you the total, not where it came from.
  16. 18 What does check_timing report, and why must you run it before trusting any slack number?Intermediate: `check_timing` (PT) scans the design for constraint problems that would make timing analysis incomplete or simply wrong — flops with no clock defined, ports with no input or output delay, generated clocks whose source pin cannot be found, and combinational feedback loops. Under-constraint is silent: a design missing constraints can still produce a fully green, all-passing `report_timing` (PT) that means nothing.
  17. 19 What is path grouping, and how does it help organize timing reports and optimization?Intermediate: `group_path` (PT) organizes timing paths into named groups — by clock, by endpoint type, or by a custom set the designer defines — so reporting and optimization tools can treat different classes of paths distinctly instead of lumping every path into one undifferentiated list. Common groupings by startpoint/endpoint type include reg2reg, in2reg, reg2out, and in2out.
  18. 20 Walk through how you would debug a path that fails by a surprising amount using report_timing increments.Intermediate: Start by reading `report_timing`'s (PT) Incr column arc by arc to find where delay accumulates unexpectedly. At each large increment, decide whether it belongs to a net arc (a wire) or a cell arc (a gate): a large net increment usually calls for a physical fix like rerouting or buffering, while a large cell increment calls for checking the cell's driving input transition and load before resizing or fixing it.
  19. 21 How would you model PLL clock jitter, and why use dynamic latency rather than uncertainty?Intermediate: Model PLL jitter as the dynamic part of clock source latency, using the `-dynamic` option of `set_clock_latency` (SDC), rather than folding it only into `set_clock_uncertainty` (SDC). Unlike uncertainty, dynamic latency affects the tool's crosstalk arrival-window calculation and is handled correctly by CRPR (clock reconvergence pessimism removal).
  20. 22 How would you set up an ideal network and control its propagation?Intermediate: Mark the source objects ideal with `set_ideal_network` (PT); the ideal property then spreads forward through combinational logic and stops at the first sequential cell. Add `-no_propagate` when only the immediate net, not its whole downstream fanout, should stay ideal.
  21. 23 How would you set interclock uncertainty between two clock domains, and when is it needed?Intermediate: Use `set_clock_uncertainty` (SDC) with `-from` and `-to`, for example `set_clock_uncertainty 2 -from [get_clocks CLKB] -to [get_clocks CLKA]`. It's needed on clock-domain-crossing paths, where the launch register and the capture register sit on different clocks.
  22. 24 Why must you query .mean/.std_dev on POCV attributes instead of the bare attribute?Intermediate: Under POCV (parametric on-chip variation), a slack or arrival value isn't one number, it's a statistical distribution, so there is no single scalar the bare attribute could return. `.mean` gives the average of that distribution and `.std_dev` gives its sigma, the spread.
  23. 25 When you pass a sequential cell to set_max_delay -from / -to, what happens under the hood?Intermediate: PrimeTime expands the cell into pins: `-from` a cell becomes each of the cell's clock input pins, `-to` a cell becomes each of its data input pins. You can see the expanded, pin-level exceptions with `report_exceptions` (PT) or `write_sdc` (PT).
  24. 26 Reconstruct the AOCV incremental derating: cell u1/u252 has late derate 1.082, early 0.924; you apply -increment -late 0.03 and -increment -early -0.03.Intermediate: An increment adds to the existing derate factor rather than replacing it, so the final late derate is 1.082 + 0.03 = 1.112 and the final early derate is 0.924 + (-0.03) = 0.894. If a sum landed below 0.0, the tool would clamp it to 0.0.
  25. 27 How would you constrain a design with both setup and hold clock uncertainty and explain the values?Intermediate: Give separate values with `set_clock_uncertainty -setup` and `-hold` (SDC), for example `-setup 0.25` and `-hold 0.10` on the same clock. Setup uncertainty is subtracted from the required time, hold uncertainty is added, and each should cover only the skew and margin relevant to its own check.
  26. 28 Explain the voltage precedence ladder. Why does it exist?Intermediate: It's the fixed tie-breaker order the tool uses when several mechanisms could each set the voltage on the same object — from a named-port override at the top down to the library's default voltage map at the bottom. A more specific, explicitly targeted setting always wins over a broad default.
  27. 29 Compare NLDM and CCS for multivoltage scaling - which is the right choice and why?Intermediate: CCS (composite current source) is the recommended Liberty model for scaling library groups: it represents the cell driver as a current source and captures nonlinear voltage dependence, whereas NLDM's (nonlinear delay model) delay and slew tables carry no real voltage dependence and drift from SPICE across a wide voltage sweep.
  28. 30 Why should you prefer the -from/-to form of an exception over the -through-plus-clock form?Intermediate: The special form — a startpoint or endpoint given as `-through` while a clock object is supplied to `-from`/`-to` — supports every valid start and end type, but it costs more to evaluate, especially on a large design. Plain `-from`/`-to` (SDC) is cheaper and should be used whenever it says what you mean.
  29. 31 Why is "case analysis propagates forward only" a fundamental limitation to keep in mind?Intermediate: Setting a constant with `set_case_analysis` (SDC) constrains only what's downstream of that pin — the tool never infers which upstream values would be logically necessary to produce it. So the constant has to be placed where its value can propagate forward to reach the logic it's meant to simplify.
  30. 32 How would you constrain a design for both setup and hold analysis at the boundary?Intermediate: Give both `-max` and `-min` input and output delays on every boundary port with `set_input_delay`/`set_output_delay` (SDC). Setup analysis uses the maximum, late external delays; hold uses the minimum, early ones — constraining only one leaves the other check with no external budget at all.
  31. 33 How do you constrain a port that receives paths from multiple clocks, and why is -add_delay needed?Intermediate: Specify each clock's delay on the port with `-add_delay` (SDC). Without it, a new `set_input_delay`/`set_output_delay` on a port removes the port's existing delay data and replaces it, so a second command without the flag would silently wipe out the first clock's budget instead of adding to it.
  32. 34 Read this exception report line and tell me what happened: From { A B C }, To D, Setup 2, Hold *, Ignored f,o.Intermediate: A `set_multicycle_path 2 -from {A B C} -to D` (SDC) was only partly applied. The `f` code means one startpoint, C, was invalid and got dropped; the `o` code means another path, A-to-D, was overridden by a higher-priority exception. Only B-to-D actually carries the multicycle value of 2.
  33. 35 Why is on-chip variation derating only meaningful once clocks are propagated?Intermediate: OCV (on-chip variation) works by derating clock latencies, giving the launch and capture clock paths different, scaled delays. With an ideal clock, there are no real propagated clock delays to derate, so before that point the equivalent margin is approximated by inflating `set_clock_uncertainty` (SDC) instead.
  34. 36 Why does a two-rail level shifter need at least eight scaling libraries?Intermediate: A level shifter spans two power domains, so its timing depends on two independent rail voltages plus temperature. Covering all three dimensions on-grid needs 2 x 2 x 2 = 8 corner combinations, against 2 x 2 = 4 for an ordinary single-rail cell that only depends on one voltage and temperature.
  35. 37 Why does the setup-check equation subtract the capture clock path but the hold-check equation also subtract it - aren't they opposite checks?Intermediate: Both equations subtract the capture clock's delay term because that delay always shifts the capture edge later in time — a single fact about the circuit. For setup, a later capture edge helps by relaxing the deadline; for hold, it hurts by widening the race window. Same term, same sign, opposite effect on margin.
  36. 38 What is the difference between reading an SDF file and reading a SPEF file?Intermediate: An SDF (standard delay format) file carries pre-computed cell and net delays that PrimeTime reads with `read_sdf` (PT) and applies directly. A SPEF (standard parasitic exchange format) file carries extracted parasitic RC data instead, read with `read_parasitics` (PT), from which PrimeTime computes the delays itself.
  37. 39 Delays and slews all look slightly off across the whole design. Why might trip points be the culprit?Intermediate: Trip points are the voltage thresholds where every delay and slew gets measured, so an unexpected threshold shifts every number in the design consistently. Confirm with `report_delay_calculation -thresholds` (PT) on a suspect arc, and `report_lib` (PT) to see which thresholds the library actually defines.
  38. 40 What happens to slack at zero, and is it something to worry about?Intermediate: Zero slack means a path meets its timing requirement with no margin left over — it is a pass, not a warning by itself. Whether zero slack is actually safe depends on what margin is already folded into the check, since a report showing exactly 0ps can hide very different amounts of real safety margin.
  39. 41 What is the difference between worst negative slack (WNS) and total negative slack (TNS), and why does signoff track both?Intermediate: Worst negative slack (WNS) is the single most negative slack value anywhere in the design — one number that tells you how bad the worst violation is. Total negative slack (TNS) is the sum of every negative slack value across all failing paths, so it tells you how widespread the problem is, not just how deep.
  40. 42 Why do pre-CTS and post-CTS timing reports show different slack for the same path?Intermediate: Before clock tree synthesis (CTS) — the step that builds the real buffered network delivering the clock to every flip-flop — the tool has no real clock wiring to measure, so it assumes an ideal clock with zero or estimated delay. After CTS, the clock has real buffers, wires, and skew, so the same path is timed against a completely different — usually less generous — set of clock arrival times.
  41. 43 How can clock skew alone create a hold violation, even with zero logic delay?Intermediate: A hold check compares how fast new data can race through the logic against how much extra time the clock gives the capturing flip-flop before its next edge. If the capturing flop's clock edge arrives earlier than the launching flop's edge — negative skew from the capture side's point of view — that time budget can go negative even when there is almost no logic delay to eat into it at all.
  42. 44 What is the difference between an intra-clock path and an inter-clock path in STA, and why does the tool treat them differently?Intermediate: An intra-clock path starts and ends on flip-flops driven by the same clock, so the launch and capture edges come from one predictable waveform. An inter-clock path crosses from one clock to a different clock, so the tool has to reason about the relationship — or lack of one — between two separate waveforms before it can even define what a valid launch-to-capture edge pair looks like.
  43. 45 Why can a path have positive setup slack and negative hold slack at the same time?Intermediate: Setup and hold are two separate checks on the same path, comparing different arrival times against different requirements — one checks whether data arrives in time for the next clock edge, the other checks whether it stays stable long enough after the current edge. A path can easily pass one check with room to spare while failing the other, because nothing forces the two results to move together.
  44. 46 How do you model early and late clock source latency with set_clock_latency?Intermediate: Source latency is the travel time from a clock's true origin — often an off-chip PLL — to the point in the design where you defined it with create_clock, and the tool cannot see that part of the path on its own. The set_clock_latency -source command with -early and -late lets you enter that travel time as a range, so setup and hold checks can each use whichever end of the range is worse for that specific check.
  45. 47 How do you constrain a clock gated by a combinational cell, using create_generated_clock -combinational?Intermediate: A gated clock — the master clock passed through an AND or OR gate for power savings — is not dividing or multiplying edges the way a flip-flop-based divider does, so it needs its own generated-clock option. The -combinational flag on create_generated_clock tells the tool to treat the output as a direct, gated copy of the master clock rather than trying to count edges.
  46. 48 How do you define a basic divide-by-2 generated clock, and what does the tool assume about its duty cycle?Intermediate: A divide-by-2 clock comes from a flip-flop that toggles once every master-clock edge, and you define it with create_generated_clock -divide_by 2 -source, pointing -source at the pin where the master clock feeds the dividing flip-flop. Because the divider toggles symmetrically on every master edge, the tool assumes a clean 50% duty cycle by default, without needing a separate waveform.
  47. 49 How do you apply different setup and hold clock uncertainty margins with set_clock_uncertainty?Intermediate: Clock uncertainty is margin the tool subtracts before deciding a check passes, and setup and hold do not always need the same amount of it. The -setup and -hold options on set_clock_uncertainty let you assign each check its own value, instead of one flat number applying equally to both.
  48. 50 How do you use a virtual clock to constrain a chip I/O interface that has no on-chip clock source?Intermediate: A virtual clock is a create_clock definition with no real source pin — it never propagates anywhere in the design, but it still gives set_input_delay and set_output_delay a -clock reference to compute setup and hold windows against. This is the standard way to constrain an interface to an external chip whose own clock never physically reaches your design.
  49. 51 What happens if you forget set_clock_groups -asynchronous between two truly unrelated clocks?Intermediate: Without that declaration, the tool still tries to time every path it can trace between the two clocks, assuming some worst-case edge alignment even if the clocks are driven by separate, unsynchronized oscillators. That worst-case alignment is often physically impossible, so the design sees a false violation with no real data-path fix, since the actual problem is a missing synchronizer, not a timing constraint.
  50. 52 How do you model asymmetric I/O timing with separate -max and -min values on set_input_delay?Intermediate: An external driver's arrival time at an input port is not always symmetric, so set_input_delay accepts separate -max and -min values instead of one flat number. The -max value feeds the setup check, since setup cares about the slowest realistic arrival, and -min feeds the hold check, since hold cares about the fastest realistic arrival.
  51. 53 What does set_output_delay actually constrain, and how is the available time computed?Intermediate: set_output_delay reserves part of the clock period for an external device's own setup and hold requirements after your output port changes, so the internal logic only gets the remaining part of the period to produce that signal. A larger output delay value leaves less time for internal logic, since more of the period is set aside for the receiving device.
  52. 54 Why must a generated clock's master clock be named explicitly with -master_clock when its source pin receives multiple clocks?Intermediate: create_generated_clock normally figures out the master clock on its own, by finding whichever clock reaches the named -source pin. When more than one clock can reach that pin — a multiplexed clock source feeding a shared divider, for example — that inference becomes ambiguous, and -master_clock has to name the intended clock explicitly.
  53. 55 How does clock uncertainty modeled with set_clock_uncertainty differ from clock latency modeled with set_clock_latency, and why are both needed?Intermediate: Clock latency tells the tool where a clock edge arrives — a position in time, set with set_clock_latency or computed from a real propagated network. Clock uncertainty is a margin subtracted around that position to cover jitter and other variation the tool cannot exactly compute, set with set_clock_uncertainty — both are needed because one answers where the edge is and the other answers how much to distrust that answer.
  54. 56 How do you define two mode-dependent clocks on the same port using create_clock -add?Intermediate: By default, a second create_clock definition on a port that already has one replaces the first. The -add option keeps both instead, which models a port reached by more than one clock through an upstream mux — but only the clock active in a given mode should actually be used, so the mux selection also needs a case analysis or a mode-specific scenario to avoid two live clocks conflicting on one node.
  55. 57 How do you fix a clock signal's polarity through an inverting or non-unate cell in the clock network with set_sense?Intermediate: The tool normally traces a clock signal's polarity automatically as it passes through the clock network, following each cell's known logic function. When a cell's function is not resolvable that way — a black-boxed cell or a non-unate function like XOR — set_sense -type clock -positive or -negative explicitly tells the tool whether the output tracks or inverts the reference clock's polarity at that point.
  56. 58 Why would you set a nonzero transition time on an ideal clock with set_clock_transition?Intermediate: An ideal clock, before it is propagated through real buffers, defaults to zero transition time — an instant edge — since the tool has no real clock network to measure slew from yet. set_clock_transition assigns a realistic nonzero rise or fall time to that ideal clock, so early setup and hold checks reflect a more realistic edge shape instead of an idealized, optimistic instant one.
  57. 59 How do you stop clock propagation at a specific pin with set_sense -stop_propagation?Intermediate: By default the tool keeps treating a signal as a clock through every downstream pin it can trace it to. When a clock-like signal legitimately feeds both real clock destinations and ordinary data logic — a test clock reused as a data mux input in some modes, for example — set_sense -type clock -stop_propagation tells the tool to stop treating it as a clock past that specific pin, so the rest of the fanout is analyzed as ordinary data.
  58. 60 What is set_case_analysis, and how does it differ from a false path?Intermediate: `set_case_analysis` (SDC) fixes a pin or port to a constant logic value for the whole analysis run, so the tool treats that input as never toggling in any mode it checks. A false path instead leaves the pin free to toggle and only removes one specific launch-to-capture pair from setup and hold checking. Because case analysis changes what the tool believes the hardware does, it can remove entire branches of logic from analysis; a false path removes only the paths you name.
  59. 61 What is a half-cycle path, and why does it need a multicycle exception?Intermediate: A half-cycle path launches on one clock edge and is captured on the very next edge of the same clock, including the opposite polarity edge, so by default the tool gives it only half a clock period instead of a full one. If the design actually only needs a new result once per full cycle, that default half-cycle check is unnecessarily strict, and a multicycle exception tells the tool to check the path over a full cycle instead.
  60. 62 How do you restrict a false path to one clock domain crossing instead of blocking every path between two clocks?Intermediate: Naming clocks with `-from [get_clocks A] -to [get_clocks B]` in `set_false_path` (SDC) declares every path between those two clocks false, in both register-to-register directions the clocks touch. To keep only one specific crossing false while other paths between the same two clocks stay checked, you name the actual startpoint and endpoint cells or pins instead of the clock objects.
  61. 63 Why would you choose a multicycle path over a false path for a signal that changes slowly?Intermediate: A false path removes a path from timing checking entirely, which is only correct if the path's timing genuinely never matters. A multicycle path instead tells the tool the real number of clock cycles available, so a slow signal that does need to meet a timing budget — just a looser one than one cycle — stays checked, with a deadline that matches how the hardware actually behaves.
  62. 64 How do you restrict a false path exception to only rising or falling clock edges?Intermediate: The plain `-from`/`-to` options in `set_false_path` (SDC) apply to a path regardless of which clock edge launches or captures it. Adding `-rise_from`, `-fall_from`, `-rise_to`, or `-fall_to` narrows the exception to only the paths that launch or are captured on that specific edge, leaving the opposite-edge paths through the same registers fully checked.
  63. 65 How do you confirm that a set_false_path exception actually matched a real path?Intermediate: The tool accepts a `set_false_path` (SDC) command even if the objects you named do not resolve to any real path in the design, and it will not warn you by default. Running `report_exceptions` (PT) or `report_timing` with the exception in place is how you confirm the command actually removed something, rather than silently doing nothing.
  64. 66 Why does a set_case_analysis value set directly on a pin win over one set on its driver?Intermediate: The tool applies a fixed priority order whenever two case analysis settings conflict on the same object: a value set directly on a pin or port always overrides a value that merely propagates to it from an upstream driver. This lets a designer override a general upstream setting for one specific downstream pin without having to change the upstream setting itself.
  65. 67 How do you apply a false path to only the setup check and leave hold fully checked?Intermediate: Adding `-setup` to a `set_false_path` (SDC) command restricts the exception to the setup check only, so the hold check on that same path keeps running normally. Without the `-setup` or `-hold` qualifier, a false path removes the path from both checks at once, which is often more than the design actually needs.
  66. 68 How do you write a multicycle path exception for a datapath that only needs a new result every three cycles?Intermediate: `set_multicycle_path -setup 3 -from ... -to ...` (SDC) grants the path three clock cycles for its setup check instead of the default one. Because that also shifts the hold check by default, you pair it with `set_multicycle_path -hold 2 -from ... -to ...` on the same path to move the hold check back to right after the launch edge.
  67. 69 What does the static value in set_case_analysis do that a plain 0 or 1 does not?Intermediate: `set_case_analysis static` (SDC) fixes a pin at a constant value without committing to whether that value is logic 0 or logic 1, which matters specifically for signal integrity analysis. A net driven by a `static` pin is treated as never switching, so it cannot act as a crosstalk aggressor or be pushed around as a crosstalk victim, the same protection a plain 0 or 1 gives for timing but stated in a way that also covers noise analysis correctly.
  68. 70 What is the difference between AOCV and POCV?Intermediate: AOCV (advanced on-chip variation) adjusts the derate factor from a lookup table based on how many logic stages or how much distance a path covers, using fixed numbers set once for the whole library. POCV (parametric on-chip variation) instead derates each individual timing arc from a statistical spread — a mean and a sigma value — read directly from the library, so the margin can differ arc by arc instead of by table lookup alone.
  69. 71 What is a derate factor, and how do early and late derates apply to opposite sides of a setup check?Intermediate: A derate factor is a multiplier the tool applies to a calculated delay to model manufacturing and environmental variation the delay calculation alone cannot see. `set_timing_derate -early` (SDC) scales delays down to model a faster-than-nominal path, and `-late` scales them up to model a slower-than-nominal path, and a single setup check actually uses both at once on opposite sides of the same path.
  70. 72 How do cell delay and net delay derates differ when you apply set_timing_derate?Intermediate: By default, `set_timing_derate -early`/`-late` (SDC) scales both the cell delays and the net delays on a path by the same factor. Adding `-cell_delay` or `-net_delay` restricts the derate to just one of the two, which matters because cell delay and net delay come from different physical sources of variation and do not need the same margin.
  71. 73 Why do larger designs move from a single flat OCV derate to AOCV tables?Intermediate: A flat derate applies the same percentage margin to a one-stage path and a fifty-stage path alike, even though random manufacturing variation tends to partly cancel out over many stages, not stack up in full. AOCV tables give a smaller derate to longer paths and a larger derate to shorter ones, recovering slack on long paths that a flat number was over-penalizing without actually giving up real coverage.
  72. 74 What does a sigma value in a POCV Liberty variation table actually represent?Intermediate: Sigma is the standard deviation of a cell delay's expected spread around its mean value if you could measure that same cell many times across normal manufacturing variation. A larger sigma means the real delay is more likely to land far from the mean; the tool combines each arc's sigma with its neighbors statistically instead of assuming every arc's delay lands at its absolute worst value at once.
  73. 75 How do you apply a named AOCV table group to one hierarchical block?Intermediate: `set_aocvm_table_group core_tables [get_cells H1]` (PT) assigns a specific, named AOCV derate table to the cells inside one hierarchical block, instead of the whole design sharing one default table. This lets a block built in a different library corner, or characterized separately, use derate data that actually matches its own construction.
  74. 76 What is clock reconvergence pessimism, and why does removing it only affect the shared clock path?Intermediate: Clock reconvergence pessimism is extra, unrealistic margin the tool adds when it assumes a launch clock path and a capture clock path vary in opposite directions, even over the portion of the clock tree they physically share. CRPR (clock reconvergence pessimism removal) corrects this only for the shared, common segment of the clock path, because that is the only part where both sides genuinely see the same physical variation at the same time.
  75. 77 How does Liberty Variation Format (LVF) let POCV derates vary by slew and load instead of one fixed sigma?Intermediate: A basic POCV model gives each timing arc one fixed sigma value, used no matter what input transition or output load that arc actually sees in the design. Liberty Variation Format (LVF) instead stores sigma as a small table indexed by input slew and output load, the same way nominal delay is already indexed, so the derate the tool applies can change arc-by-instance based on real operating conditions.
  76. 78 Why do you still need on-chip variation margin even after running timing at every PVT corner?Intermediate: A PVT corner models variation between chips or across a whole die — one chip running slightly hot and slow, another cool and fast — using one fixed set of conditions for the entire design in that run. On-chip variation (OCV) margin instead models variation between two points inside the very same chip in the very same run, which a corner, by definition, holds constant.
  77. 79 What is crosstalk delay, and how is it different from crosstalk noise?Intermediate: Crosstalk delay is a timing effect: a neighboring wire switching at the same time pushes out or pulls in your signal's arrival time, changing when it gets there. Crosstalk noise is a voltage effect: a neighbor's switch bumps a quiet, steady wire enough that a downstream gate can briefly misread it, even though nothing on that wire was supposed to switch at all.
  78. 80 How does total negative slack change when you turn on signal integrity analysis?Intermediate: Turning on signal integrity (SI) analysis usually makes total negative slack (TNS) worse, because the tool now adds a delta delay for every net whose neighbors can switch at a similar time, instead of assuming clean, unaffected wires. Some paths can also improve slightly, since a neighbor switching the opposite direction can pull a signal in early instead of pushing it out.
  79. 81 What is a timing window, and why does crosstalk analysis need it?Intermediate: A timing window is the range of time during which a signal could plausibly switch, given the earliest and latest arrival times the tool has already computed for it. Crosstalk analysis needs timing windows because two nets only affect each other if their windows actually overlap — a neighbor that always switches hours before or after your signal is not a real aggressor, no matter how much capacitance couples them.
  80. 82 Why does a switching aggressor net push out or pull in a victim signal?Intermediate: A switching aggressor net pushes out or pulls in a victim through the coupling capacitance between them: current flowing through that shared capacitance either fights against the victim's own edge or helps it along, depending on whether the two nets switch in the same direction or opposite directions at close to the same time. The result is a real change in the victim's arrival time, not just a voltage bump.
  81. 83 What does the si_enable_analysis variable actually turn on in PrimeTime?Intermediate: Setting the si_enable_analysis variable to true tells PrimeTime to compute crosstalk delta delay for every net during timing analysis, using the coupling capacitance in the annotated parasitics, instead of timing each net as if it had no neighbors. It is a global switch: once set, it applies to the whole analysis, not to one net or one path at a time.
  82. 84 How do you read a report_si_bottleneck report to find the worst nets?Intermediate: The `report_si_bottleneck` (PT) command ranks nets by how much crosstalk delay or noise they contribute across every scenario, then prunes duplicates so you get one unique, sorted list of the worst offenders instead of scrolling through a separate report per scenario. You read it top to bottom, fixing the highest-cost net first, since it usually touches the most violating paths per unit of repair effort.
  83. 85 Why do shielded or wider-spaced nets see less crosstalk than tightly packed signal nets?Intermediate: Coupling capacitance between two wires grows as they run closer together and for a longer parallel distance, and shrinks quickly as the spacing between them increases. A shield — a grounded or fixed-value wire placed between a signal and its neighbor — gives the coupling current somewhere to go that is not the victim net, so both wider spacing and shielding cut crosstalk by directly reducing the capacitance the aggressor can act through.
  84. 86 What is capacitive coupling percentage, and how does it affect delay calculation?Intermediate: Capacitive coupling percentage is the share of a net's total capacitance that comes from coupling to neighboring nets, rather than from ground or fixed-reference capacitance. A net with a high coupling percentage is dominated by its neighbors' switching behavior, so its delay is far more sensitive to what nearby aggressors do than a net whose capacitance is mostly grounded.
  85. 87 How does PrimeTime decide which nets actually need crosstalk analysis?Intermediate: PrimeTime starts from every net that has coupling capacitance to at least one neighbor and an overlapping timing window with that neighbor, then narrows the list using explicit include and exclude commands the designer supplies for cases the tool cannot infer on its own, such as two nets that are physically close but logically guaranteed never to switch together. Without SI enabled at all, the tool skips crosstalk analysis entirely and times every net as an isolated wire.
  86. 88 What is a scenario in multi-corner, multi-mode analysis?Intermediate: A scenario is one complete, self-contained timing setup: a single combination of an operating mode (its own SDC constraints, like functional or test mode) and a single PVT corner (its own library, operating condition, and parasitics). PrimeTime analyzes each scenario as if it were a fully separate design, then merges the results, because a design's real behavior depends on which mode and which corner it is actually running under at any given moment.
  87. 89 How do you switch between scenarios during an interactive PrimeTime session?Intermediate: The `current_scenario` (PT) command changes which scenario subsequent commands apply to, whether that is one specific scenario, a chosen subset, or every scenario at once with the `-all` option. This matters because most PrimeTime reporting and analysis commands act on whatever scenario currently has command focus, not on the whole design by default.
  88. 90 Why doesn't signoff run every operating mode against every PVT corner?Intermediate: Running every mode against every corner is the safest possible coverage, but it is also the most expensive: each additional scenario costs real machine time and license usage to analyze, and many mode-corner combinations are physically impossible or already known to be dominated by a different combination. Teams prune the full cross product down to the combinations that can actually happen and that actually stress a check, rather than paying for scenarios that provide no new information.
  89. 91 What is HyperScale, and why use it instead of one flat run for a large chip?Intermediate: HyperScale is a PrimeTime capability for analyzing a very large design as a set of smaller blocks with lightweight timing models standing in for each block's internals, distributed across multiple machines, instead of loading the entire flattened netlist into one process. It exists because a full-chip flat run on a large SoC can outgrow the memory and runtime budget of a single machine long before it outgrows the design itself.
  90. 92 What does an ETM actually hide, and what timing information does it keep at the block boundary?Intermediate: An extracted timing model (ETM) hides everything happening inside a block — its gates, its internal nets, its internal paths — and keeps only the input-to-output timing arcs a neighboring block actually needs: how long a signal takes to cross the block, and what capacitance or drive strength it presents at each boundary pin. It is built so a top-level run can time paths that pass through the block correctly, without ever loading the block's real netlist.
  91. 93 What information does a scenario need besides a corner, library, and clock definition?Intermediate: Beyond the PVT corner's library and the clock's SDC definition, a complete scenario also needs its own operating condition (the exact voltage and temperature point within the corner), its own set of annotated parasitics matching that corner's extraction, and its own mode-specific constraints such as case analysis settings and exceptions. Leaving any one of these tied to a different scenario's data, instead of the scenario's own, produces a result that looks complete but times the design under a mismatched, inconsistent set of assumptions.
  92. 94 How do you report timing results across all scenarios at once in PrimeTime?Intermediate: The `report_global_timing` (PT) command summarizes worst-case timing across every active scenario in one view, instead of requiring a separate report per scenario that a designer would have to compare by hand. It gathers each path's result from whichever scenario stresses it hardest and presents a single, ranked summary of the design's actual worst-case timing status.
  93. 95 What is the difference between a flat and a hierarchical timing run?Intermediate: A flat timing run loads a design's entire netlist into one analysis, with every gate and wire visible to the tool at once, regardless of which block it belongs to. A hierarchical run instead analyzes some blocks using compact stand-in models — an extracted timing model or a HyperScale boundary model — instead of their full netlists, trading a small amount of representational detail for a large reduction in memory and runtime.
  94. 96 How do you set an initial timing budget for a block before its real implementation exists?Intermediate: Before a block has real gates and wires, its portion of a top-level path's available time is estimated from the block's expected size, pin count, and role in the path, then written as a placeholder budget — an artificial input or output delay constraint on the block's boundary — so the block team can start implementation against a concrete target instead of waiting for the rest of the chip to be built first.
  95. 97 Why does a clean graph-based timing report still need a path-based rerun before signoff?Intermediate: Graph-based analysis (GBA) times every stage of every path using the single worst-case delay for that stage, so it never actually walks one real path start to finish. That worst case might come from a completely different path than the one being reported, which stacks extra pessimism onto the number PrimeTime prints. Path-based analysis (PBA) re-times the specific path in question using its own real delays, so signoff only trusts a report once the paths that look like they fail under GBA have been re-checked with PBA.
  96. 98 How do you read a clock skew report from report_clock_timing?Intermediate: Clock skew is the difference in arrival time of the same clock edge at two different flip-flops, and it can help or hurt a setup or hold check depending on its sign. `report_clock_timing -type skew` (PT) lists, for a chosen clock, the launch and capture arrival times at the worst pair of registers and the skew between them, so you can see whether the clock network itself is adding or removing margin on a path.
  97. 99 What does an interclock skew report tell you that a single-clock skew report does not?Intermediate: A single-clock skew report only compares arrival times of the same clock at different flops, but many real paths launch from one clock and capture on a different one. `report_clock_timing -type interclock_skew` (PT) reports the timing relationship between two distinct clock edges at the point a path actually crosses between them, which is the number the setup and hold checks on that crossing actually use.
  98. 100 How do you get PrimeTime to report a hold check instead of a setup check with report_timing?Intermediate: By default `report_timing` (PT) reports the setup (max delay) check for the worst path, so a designer chasing a hold problem can stare at the wrong check without realizing it. Adding `-delay_type min` (PT) tells the command to report the minimum-delay, hold-side check instead, which uses a different required time and often a different worst path entirely.
  99. 101 What does the -nworst option on report_timing show you that the default report does not?Intermediate: By default `report_timing` (PT) prints only the single worst path for the endpoints it is scoped to, which hides every other path that is also close to failing. `-nworst N` (PT) reports the N worst paths per endpoint instead of one, so a designer can see whether a violation is an isolated path or the tip of a cluster of similar failures.
  100. 102 How do you find out that a false path or multicycle exception never matched any real path?Intermediate: Writing `set_false_path` or `set_multicycle_path` (SDC) with a typo in a pin, instance, or clock name does not raise an error, PrimeTime simply applies the exception to zero paths and stays silent. `report_exceptions -ignored` (PT) lists every exception in the design that matched nothing, which is the only reliable way to catch this before it hides a real violation.
  101. 103 When must you force a full timing update with update_timing -full instead of trusting the incremental one?Intermediate: PrimeTime normally re-times only the parts of the design that changed since the last update, which is fast but relies on the tool correctly tracking every dependency. `update_timing -full` (PT) throws away that incremental state and recomputes timing for the entire design from scratch, which is the safer choice after a change the incremental engine might not fully track, such as a library swap or certain low-level scripted edits.
  102. 104 Why do engineers save a PrimeTime session with save_session instead of re-running the whole flow?Intermediate: Reading in a large netlist, linking libraries, applying SDC, and running the first `update_timing` (PT) can take a long time on a real design, and repeating all of it just to check one more report wastes that time every session. `save_session` (PT) writes the fully loaded and timed design state to disk, and `restore_session` (PT) brings it back almost immediately, so a designer can pick up exactly where the last session left off.
  103. 105 How does set_host_options -max_cores speed up timing updates on a large design?Intermediate: A single-core PrimeTime run processes the design's timing update one operation at a time, which becomes the bottleneck on a design with millions of instances and many scenarios. `set_host_options -max_cores N` (PT) lets PrimeTime split timing updates and parasitic reads across N cores on the same machine, so the same update finishes in a fraction of the time.
  104. 106 What does report_global_timing show that checking individual failing paths does not?Intermediate: Reading one `report_timing` (PT) result at a time tells you about a single path, but it says nothing about whether the design as a whole is converging toward closure or drifting further from it. `report_global_timing` (PT) summarizes the overall timing closure state across the design, how many endpoints are met, how many are violating, and by how much in aggregate, giving a single closure snapshot instead of a path-by-path picture.
  105. 107 What timing checks must be clean before a design can tape out?Intermediate: Tapeout signoff is not one number, it is a checklist that every setup and hold check passes across every signoff corner and mode, every design-rule check like max transition and max capacitance is clean, and every endpoint in the design is actually constrained. Missing any one item on that list, even while the main slack number looks clean, means the design is not ready to tape out.
  106. 108 How do you swap a cell to a faster drive strength with size_cell during a PrimeTime ECO?Intermediate: When a path fails setup because one cell along it is too slow, replacing that cell with a stronger drive-strength version of the same function is often the cheapest fix, since it changes delay without touching placement or routing. `size_cell` (PT) does exactly this inside an ECO session, swapping a named instance to a different library cell while PrimeTime checks the new cell fits the same footprint and pin function.
  107. 109 When do you insert a buffer with insert_buffer instead of resizing an existing cell?Intermediate: Resizing an existing cell only helps when a stronger version of the same function exists in the library and fits the same footprint, which is not always true, especially for a hold fix that needs a small, precise amount of extra delay. `insert_buffer` (PT) adds a brand-new buffer cell at a driver pin during an ECO, which is the standard way to add delay a resize cannot provide, or to fix a net with excessive load a single cell swap cannot absorb.
  108. 110 What does report_eco show you after a round of PrimeTime ECO fixes?Intermediate: There is no `report_eco` command in PrimeTime, so this question has a false premise. Before fixing, `report_eco_options` (PT) confirms the settings the fixer is allowed to use, and `report_eco_library_cells` (PT) lists the candidate cells it can swap in. After fixing, the actual log of what changed comes from `write_changes -format text` (PT), which prints every size_cell and insert_buffer edit applied in the session as a readable change list.
  109. 111 Why do you generate an SDF file with write_sdf as part of timing signoff?Intermediate: Static timing analysis confirms the design meets timing inside PrimeTime, but other tools in the flow, gate-level simulation, other STA tools used for cross-checking, or a customer's own verification, need the same delay information in a portable, standard format. `write_sdf` (PT) exports PrimeTime's computed cell and net delays as a Standard Delay Format file, which is the accepted handoff format for carrying signed-off timing outside PrimeTime itself.
  110. 112 Why can a design pass timing at the typical corner and still fail signoff at a corner you didn't check?Intermediate: A single corner combines one process, one voltage, and one temperature assumption, and different corners can make different checks the worst one, a fast, low-voltage corner tends to be worst for hold while a slow, high-voltage corner tends to be worst for setup. A design that only reports clean at the typical corner has simply never been checked against the corner where its real worst violation would show up.
  111. 113 Why must post-ECO timing be re-extracted with fresh parasitics instead of reusing the pre-ECO SPEF?Intermediate: A SPEF file records the resistance and capacitance PrimeTime uses to compute net delay, and it describes one specific physical layout. Once an ECO adds a buffer, resizes a cell, or reroutes a net, the physical layout has changed, so the old SPEF no longer describes the real chip, and any timing report built from it is describing a design that no longer exists.
  112. 114 Why does an ECO that fixes one endpoint's hold violation sometimes create a new one nearby?Intermediate: A hold fix, whether a resized cell or an inserted buffer, adds delay onto a net that other logic may also depend on, and that added delay can push a neighboring path that used to have a little hold margin into a violation of its own. Fixing one endpoint in isolation, without checking what else shares that net or driver, can trade one violation for another instead of clearing it.

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