IntermediateQuestion 32 of 112

How would you constrain a design for both setup and hold analysis at the boundary?

From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide

By Tabish Iqbal, who has 9+ years of VLSI Physical Design experience

Short Answer

Give both -max and -min input and output delays on every boundary port with set_input_delay/set_output_delay (SDC). Setup analysis uses the maximum, late external delays; hold uses the minimum, early ones — constraining only one leaves the other check with no external budget at all.

A boundary input port with separate -max and -min set_input_delay arrows feeding the setup check and the hold check on the first internal register respectively — Technical Reference DiagramHow would you constrain a design for both setup and hold analysis at the boundary?

Technical Reference DiagramHow would you constrain a design for both setup and hold analysis at the boundary?

Technical Explanation

Setup and hold are separate checks that consume opposite extremes of the external delay range, so every boundary port needs both.

On inputs: set_input_delay -max (SDC) gives the maximum external delay, feeding the setup check on the internal path starting at that port; -min gives the minimum external delay, feeding the hold check.
Why both, not one shared value: a single number can apply to both if the external timing is genuinely fixed, but for accurate analysis the max and min external delays are usually set separately, because the real external path has a range, and setup and hold each need their own end of it.
On outputs: set_output_delay -max gives the longest external path plus the external register's setup requirement, feeding the setup check on the internal path ending at that port; -min gives the shortest external path minus hold, feeding the hold check.
Why setup and hold pull from opposite ends: setup asks whether the latest-arriving data still meets the capture register's setup requirement, so it uses maximum delays throughout; hold asks whether the earliest-arriving data still clears the hold requirement, so it uses minimum delays throughout.
The completeness rule people miss: every boundary port needs both a min and a max, or one of the two checks is left effectively unconstrained on paths touching that port. Set only -max, and the hold paths at that port have no early external budget at all — the tool has nothing to check hold against there.

Common Mistake

The Trap: setting only -max input/output delays on a boundary port because that's the value the interface spec happened to hand over first.

A designer receives a "worst-case external delay" number from the block's integration partner and applies it as -max only, treating hold as something to worry about later.
Later never comes explicitly, so the port's hold paths are analyzed against an implicit minimum of zero delay, which understates the real early-arrival risk and can hide a genuine boundary hold violation until it shows up post-silicon.

Follow-up Question & Model Response

If the external interface really does have a single, fixed delay with no range, do you still need to write both -max and -min?

Candidate Model Response: Yes, even a fixed external delay should be written for both, because leaving one off doesn't mean "use the same value" — it means the tool assumes no delay at all on that side for the check you skipped. Writing the same number for both -max and -min costs nothing and makes the intent explicit in the SDC, whereas omitting one relies on every future reader knowing the delay is fixed and remembering to add it back if the interface later gains a real range. It also protects the constraint if that assumption changes without the SDC being revisited.

Practical Example

A boundary input DIN connects to an external SPI controller whose datasheet gives a delay range of 1.2 ns to 2.1 ns relative to the shared 100 MHz clock. The team writes set_input_delay -max 2.1 -clock CLK [get_ports DIN] and set_input_delay -min 1.2 -clock CLK [get_ports DIN] (SDC). report_port -input_delay [get_ports DIN] (PT) then shows both values in effect, and report_timing -delay_type min -to [get_pins reg1/D] (PT) confirms the hold check on the first internal register is evaluated against the 1.2 ns minimum, not zero.

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