Explain how MIS, CRPR, and the hold check interact on a short clock-adjacent data path.
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Both effects change the same number — min delay, which is the value the hold check compares against the clock's arrival. Multi-input switching (MIS, a faster delay the library allows when several gate inputs switch together) shortens the data side, so data arrives earlier. Clock reconvergence pessimism removal (CRPR) adjusts the shared portion of the launch and capture clock paths. The hold check then compares the MIS-shortened arrival against the CRPR-adjusted capture time — and the two effects do not push the same way, so both need to be modeled correctly to get the true margin.
Technical Explanation
A hold check on a short, clock-adjacent path pulls in two separate PrimeTime mechanisms that both touch min delay, the quantity a hold check consumes.
- What MIS changes: multi-input switching (MIS) (PT) is a library-characterized speed-up factor applied to a gate's delay when more than one input switches at once — the classic case is a wide NAND or NOR gate in a decoder. The tool scopes this to minimum-delay (hold) checking only, because a short data path is exactly where a few picoseconds of speed-up matters.
- Why that tightens hold: hold fails when data arrives too early relative to the clock. MIS shortens the co-switching gate's min delay, so data really can arrive earlier than a single-input-switching model predicts, and the hold check gets stricter.
- What CRPR changes: clock reconvergence pessimism removal (CRPR) finds the physical segment the launch and capture clock trees share before they diverge, and removes the double-counted on-chip variation (OCV) derating on that shared segment.
- Why CRPR's direction varies: unlike MIS, CRPR does not push one way — it can loosen or tighten the hold check depending on how much clock tree the launch and capture paths share and how the derates land on each side.
- How they combine: the hold check compares the MIS-adjusted data arrival against the CRPR-adjusted capture edge. Each answers a different question about the same comparison, so neither is optional.
- What breaks if you skip one: disable MIS on a design with real decoder-style co-switching and the reported margin is optimistic — silicon will be faster than the model. Disable or misconfigure CRPR and the check keeps leftover OCV pessimism, which can report a violation that is not real.
- Why it matters most on short paths: a long setup path absorbs a few picoseconds without changing the verdict. A short clock-adjacent hold path often has only tens of picoseconds of margin, so this exact combination decides real violation versus phantom.
Common Mistake
The Trap: treating a hold violation on a short adjacent-flop path as purely a CRPR credit problem and re-running report_crpr (PT) in a loop, without ever checking whether MIS is enabled for the library cells on the data side.
- The tool never widens a MIS speed-up back out on its own — if
si_enable_multi_input_switching_analysis(PT) was left off, the reported hold slack is already too generous, and no amount of CRPR tuning corrects that. - Conversely, assuming any hold pass is real without confirming CRPR ran on the shared clock segment leaves reviewers unable to tell whether the margin came from real silicon behavior or from unmodeled pessimism removal.
Follow-up Question & Model Response
"If report_timing shows a comfortable hold pass on this path, what would make you distrust that number specifically because of MIS?"
Candidate Model Response: I would check whether the data-path cells are library cells that qualify for MIS — wide NAND/NOR-style gates with multiple co-switching inputs — and whether si_enable_multi_input_switching_analysis (PT) was actually set for that run. A comfortable pass on a path with no MIS-eligible cells is trustworthy at face value. A comfortable pass on a path that does have MIS-eligible cells, run without MIS enabled, means the tool used the slower single-input-switching delay, so the real silicon path is faster and the true margin is smaller than reported — possibly negative. I would re-run with MIS enabled and re-check before trusting the slack.
Practical Example
A 4-input NAND gate feeds a hold-critical path between two adjacent flops on a 400 MHz decode clock, CLK_DEC, that launch and capture through a shared 3-buffer clock trunk. With MIS disabled, the library's single-input-switching delay for that NAND is 95 ps, and report_timing -delay_type min shows +18 ps hold slack. Enabling si_enable_multi_input_switching_analysis (PT) with the advanced analysis mode drops the same arc to 71 ps once the tool confirms the other three inputs' arrival windows overlap, tightening slack to −6 ps — a real violation the single-input model hid. Running report_crpr (PT) on the same path separately shows a 9 ps credit from the shared trunk, which is already folded into both numbers above; it does not offset the MIS-driven drop, because the two mechanisms compute against different sides of the check.
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