Explain why the SDF PORT construct and multidrive alignment are both about clock networks, yet solve different problems.
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Both features exist because a clock mesh or spine has huge numbers of nearly identical nets, but they solve different problems. The PORT construct, enabled with sdf_enable_port_construct, shrinks SDF file size by collapsing near-identical INTERCONNECT delays into one PORT statement. Multidrive alignment, enabled with sdf_align_multi_drive_cell_arcs, forces one worst-case delay onto parallel driver cell arcs so a downstream simulator does not fail on ambiguous multidriven timing โ and unlike the PORT construct, it is deliberately pessimistic.
Technical Explanation
A large clock mesh or spine network is where both problems appear together, because that is where massive net and driver parallelism exists โ but the two SDF reduction features attack different parts of it.
- The problem the PORT construct solves: file size. A mesh has huge numbers of near-identical
INTERCONNECTdelay statements.sdf_enable_port_construct(PT), default false, letswrite_sdf(PT) replace groups of them with a single SDF 3.0PORTstatement wherever delays fall withinsdf_enable_port_construct_threshold(PT), default 1 ps. - How much it actually compresses. In the guide's own four-driver, four-load mesh example, 16 individual
INTERCONNECTstatements collapse into 4PORTstatements once delays are close enough to merge. - Why that compression is essentially lossless within its threshold. The PORT statement keeps the merged delay range accurately reflecting the near-identical original values โ a representation change for file size, not a deliberate loss of accuracy.
- The problem multidrive alignment solves: simulator correctness. A net driven by multiple parallel drivers with slightly different cell-arc delays can trigger a downstream simulation failure over ambiguous multidriven timing.
sdf_align_multi_drive_cell_arcs(PT), default false, unifies those arcs to one value when the cells are combinational, single input/output, and withinsdf_align_multi_drive_cell_arcs_threshold(PT), also default 1 ps. - How the unification is chosen, deliberately pessimistically. The tool takes the worst delay across the parallel drivers โ the minimum of the min delays and the maximum of the max delays โ and assigns that single value to every driver's arc.
- Why that pessimism is a feature, not a defect, for this purpose. The guide is explicit that this SDF is meant for simulation, and warns against reading it back into PrimeTime for timing analysis, because the data is deliberately pessimistic โ built for consistent simulator behavior, not PrimeTime's own accurate timing view.
- So the two features are layered, not redundant. Both can be enabled together on the same mesh; PrimeTime aligns the cell arcs first, then represents the resulting net arcs with PORT statements where the aligned values are close enough.
- Why they both cluster on clock networks specifically. Massive parallelism creates both the file-size problem and the multidrive-ambiguity problem at the same time, which is why both variables live in the same clock mesh/spine SDF-reduction section of the guide rather than being generic settings.
Common Mistake
The Trap: enabling sdf_align_multi_drive_cell_arcs (PT) to generate a simulation-safe SDF, then reading that same SDF back into PrimeTime for further timing analysis or ECO work.
- The guide is explicit that the aligned data is deliberately pessimistic, so re-reading it into PrimeTime for timing purposes reports a worse-than-real delay on every arc the alignment touched.
- The correct practice is generating two SDF views for two purposes: an aligned one for simulation, and the tool's own unaligned timing data for anything PrimeTime itself signs off on.
Follow-up Question & Model Response
"If a mesh net is driven by three-state buffers, does either reduction feature still apply?"
Candidate Model Response: No, not fully. The PORT construct explicitly excludes parallel nets driven by three-state buffers from being combined, and multidrive alignment likewise does not align cell delays when the common net is driven by three-state buffers. Both features are scoped to the ordinary combinational parallel-driver case, so a three-state-driven mesh net keeps its full, unreduced INTERCONNECT and individual cell-arc representation regardless of these settings.
Practical Example
A clock spine has four parallel buffers, B1 through B4, all feeding a shared load pin with cell delays ranging from 1.0/1.3 ns to 1.2/1.5 ns (min/max). With sdf_align_multi_drive_cell_arcs (PT) enabled and delays within the 1 ps-scaled threshold range for this normalization, PrimeTime aligns all four drivers to the worst combination, 1.0 ns minimum and 1.5 ns maximum, so the simulator sees one consistent delay regardless of which buffer's path it traces. Separately, sdf_enable_port_construct (PT) on the same spine's fan-out nets collapses what would have been dozens of near-identical INTERCONNECT statements into a handful of PORT statements. The engineering team keeps this aligned, PORT-compressed SDF strictly for gate-level simulation, and signs off timing separately from PrimeTime's own unaligned report_timing (PT) data.
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